Category: Hardware
Product Number: AD9910
Hello Team,
I am using the AD9910 evaluation board and observing a frequency offset in the SYNC_CLK and consequently in the DDS output frequency.
My configuration is intended to provide:
- SYSCLK = 1 GHz
- Expected SYNC_CLK = 250.000000 MHz (SYSCLK/4)
- Measured SYNC_CLK = 249.981124 MHz
- SYNC_CLK error = approximately −18.876 kHz (−75.5 ppm)
249.981124 MHz × 4 = 999.924496 MHz
My questions are:
- What could cause this ~75 ppm offset in the AD9910 system clock?
- Can the AD9910 internal PLL introduce a fixed frequency offset of this magnitude even when PLL lock is indicated?
- Is there any recommended method to calibrate or compensate for this error?
- For a frequency-critical application, would you recommend using an external high-accuracy TCXO/OCXO instead of the evaluation board clock source?
The frequency measurement was taken directly at the AD9910 SYNC_CLK output.
Any suggestions on what measurements or PLL/reference-clock parameters I should check would be greatly appreciated.
Thank you.
