AD9914 Clocking problem

Question

I made custom board with AD9914 
 I want to use AD9914 with 3.4GHz clock 
 As source I have STW81200 on board. I am sourcing signal from STW81200 to REF_CLK in differential mode. STW81200 has differential output power at 3.4GHz about 10dBm(so it about 1V peak) 
 As I see from datasheet without any programming AD9914 should output refclk/24 on SYNC_CLK 
 But on SYNC_CLK I see noise and random pulses(if signal is sourced from oscillator) 
 Also I tried to source signal from external generator(powers from 0 to 20dBm and frequencies 100-3400MHz) result is the same. 
 On AD9914 I also see random pulses. I also managed to program part. And now it seems that output frequency is changing according to programmed FTW. But it seems because of wrong ref_clk, output also random pulses but when I program smaller FTW I see changes in this random pulses 
 
 What can be wrong? 
 
 P.S. AD9914 is wired as in reference schematic except there are no components on pll charge pump 
 Please advise 
 
 Also additional question. What should be power level of reference signal at 3.4GHz? For now STW81200 drivers can source in differentioal about 10dBm. But I see that in datasheet input impedance is highly capacitive for 3.4GHz(1pF). Do I need some matching AD9914 to work with my reference signal?

Jules.Nikko · Accepted Answer

Hi JWizard88 , 
 The AD9914 requires DAC calibration after every power-up and whenever the system clock changes. Without it, the datasheet explicitly states "Failure to calibrate may degrade performance and even result in loss of functionality." This is very likely why you see random pulses instead of a clean SYNC_CLK. 
 As for your missing PLL charge pump components, this is fine. As long as your PLL is disabled CFR3[18] = 0. The PLL loop filter pin should still have the recommended 560 pF cap to ground even if the PLL is disabled, or at minimum be left floating/grounded. Verify is this is not causing issues. 
 As for your REF_CLK input level at 3.4 GHz, from the data sheet specs, required differential input is as follows: 
 
 Your 10 dBm (~ 1V peak, ~2V p-p differential) is above the 1.5 Vp-p max spec. This might be likely one of the causes as well. You are overdriving the input. At 3.4 GHz with 1 pF input capacitance, the capacitive reactance is 47 ohms, so the high source impedance mismatch and overdrive could cause the input buffer to clip. 
 As the power level, usually I use 0dBm. 
 All the best, 
 Jules)

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AD9914 Clocking problem

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