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Partial external control of the AD9914

Thread Summary

The user asked about the correct procedure for switching from full USB control to partial external control on the AD9914 evaluation board. The final answer emphasized that headers P205 (and possibly P203/P204) should never be swapped while the board is powered, as this can cause latch-up and damage the AD9914. The safe procedure involves powering off the board, changing the header position, and then powering back on. The 74LVC541APW buffers are not tri-statable, and the USB microcontroller does not require a reset upon reconnection. The AD9914 User Guide Wiki Page provides additional details on header functions.
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Category: Hardware
Product Number: AD9914

Hi,

I'm using the AD9914 evaluation board, and I need clarification on the correct/intended procedure for switching from full USB control to partial external control.

Application context:
My workflow requires two phases per cycle:

  1. Program all internal registers over USB (FTW, DRG step/rate registers, CFR1/CFR2, profile registers, etc.) using the eval board GUI.
  2. Hand off control of DRCTL and PS0 to an external pattern generator for pulse-to-pulse triggering of the digital ramp generator, without the onboard USB microcontroller interfering on those lines.
    The pins DROVR, DRHOLD, PS1 and PS2 are pulled to ground to ensure all externally controlled signals are not floating.

What I've observed from the schematic:
The P205 header block sits between U200 (USB microcontroller) and the AD9914 control/programming pins, and appears to be the intended isolation point. I'm currently removing/disabling P205 before starting my external pattern to avoid bus contention, and this has worked empirically — but I don't have documentation confirming this is the correct mechanism.

Specific questions:

  1. Is physically tri-stating/removing P205 (and possibly P203/P204) the ADI-recommended way to release the AD9914's control pins for external drive, or is there a GUI/software command that should be issued first (e.g., an "external control" or "release bus" mode) before pulling the header?
  2. Is there a required sequence — e.g., must the final IO_UPDATE be issued and registers latched before removing the jumper, or does the AD9914 need to be held in a defined state while the jumper is pulled, to avoid glitching DRCTL/PS0/IO_UPDATE?
  3. Are U202/U203/U204 (the 74LVC541APW buffers on DRCTL/IO_UPDATE per the schematic) actually tri-statable outputs controlled by the P20x headers, or is the header simply breaking a physical trace connection? This matters for understanding whether any pin floats to an undefined level (no pull resistors are shown on these lines) when the header is removed.
  4. What is the safe procedure to reconnect P205 and resume USB control afterward — does U200 need a reset/re-enumeration, or does it resynchronize automatically?
  5. Is this handoff procedure documented anywhere? (I haven't found it in the AD9914 datasheet)

Any confirmation from ADI application engineers or others who've used this board in a hybrid USB/external-control configuration would be greatly appreciated.

Thanks,
wmcher

  • Hi  ,

    1. Is removing P205 the correct isolation method?
    Yes. The P20x headers on ADI DDS eval boards are specifically designed as isolation/handoff points between the USB microcontroller (U200) and the AD9914 control pins. There is no GUI "release bus" command. The microcontroller has no tri state firmware mode for these lines. Physically removing the jumper shunts on P205 (and P203/P204 as needed for IO_UPDATE/PS pins) is the correct procedure.

    2. Required sequence before removing the header?

    Yes , you must issue a final IO_UPDATE and confirm register latching before pulling the header. The required sequence is:

    1. Program all registers (FTW, DRG limits/step/rate, CFR1/CFR2, profiles) via the GUI.
    2. Issue IO_UPDATE (via GUI "Write" or explicit IO_UPDATE button). This transfers I/O buffer contents to active registers. 
    3. Confirm DRG is enabled: CFR2[19] = 1, DRG destination bits set, no-dwell bits configured as desired. All latched by that IO_UPDATE.
    4. Then remove P205 jumpers.
    5. Connect your external pattern generator to DRCTL (and PS0 if needed).

     If you pull the header mid IO_UPDATE assertion or while a register write is in progress, you risk partial register loading. The AD9914 latches on the rising edge of IO_UPDATE, so ensure IO_UPDATE has returned low before disconnecting.

    3. Are U202/U203/U204 (74LVC541APW) tri-statable, or is the header just a trace break?

    The 74LVC541APW is a unidirectional octal buffer with an active-low output enable (OE). On the AD9914 eval board:

    - The P20x headers break the physical connection between the buffer outputs and the AD9914 input pin. They are not controlling the OE pin of the buffers.
    - When you remove the jumper, the AD9914 side of DRCTL/IO_UPDATE/PS0 will float since there are typically no on board pull up/pull down resistors on these lines.

    Your observation that you're grounding DROVR, DRHOLD, PS1, PS2 is correct and critical. You should also ensure:

    - DRCTL has a defined state from your pattern generator before/immediately after removing the jumper (or add an external pull-down to prevent a glitch that could trigger a ramp).
    - IO_UPDATE should be pulled low externally (or driven low by your pattern generator) to prevent spurious register updates.

    4. Reconnecting P205 and resuming USB control
    - U200 does NOT need a reset or re-enumeration. The USB microcontroller maintains its connection to the host PC regardless of the header state.

     Safe reconnection procedure:
    1. Ensure your external pattern generator is tri-stated or disconnected from the DRCTL/PS0/IO_UPDATE lines (to avoid bus contention when you reconnect the buffer outputs).
    2. Re-insert P205 jumpers.
    3. In the eval board GUI, perform a register readback or simply re-write your configuration and issue IO_UPDATE to re-synchronize the GUI state with the hardware.
    - The GUI will immediately regain control, no reset needed.

    5. Is this handoff procedure documented?
    Not explicitly in the AD9914 datasheet (Rev. G). The datasheet only mentions the eval board by part number (AD9914/PCBZ) on page 48 with no procedural detail. The procedure would be in:

    - AD9914 User Guide Wiki Page describes P203/P204/P205 header functions but focuses on basic setup. 

    All the best,

    Jules

  • Follow-up on partial external control of the AD9914 — we lost a chip to this and traced it to a misunderstanding of P205.

    We pulled it live (switching P205 from DISABLE to ENABLE) and the AD9914 failed instantly: 3.3 V I/O domain shorted, 1.8 V core still healthy, U203 and the USB controller both survived — consistent with latch-up triggered by the header/enable event.

    Can I confirm if I can remove any of the P20x headers to switch control of the signals when the board is fully powered (3.3V and 1.8V inputs connected, USB connector plugged in), or should I power off the board fully before changing any of the P20x headers?

    Thanks,

    wmcher

  • Hi  ,

    Never swap the P20x headers. Always power off the board completely first.

    When you plug/unplug a header while powered, the mechanical contact bounce creates voltage spikes on the AD9914's I/O pins that exceed its absolute maximum ratings. This triggers latch-up, a permanent short in the 3.3V I/O domain that kills the chip instantly.

    Safe procedure:

    1. Program registers via USB, issue IO_UPDATE
    2. Power off everything (3.3V, 1.8V, and USB cable)
    3. Change the P205 header position
    4. Connect your external signals with defined idle states
    5. Power back up and re-program registers 

    All the best,

    Jules

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