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AD9954 Production
The AD9954 is a direct digital synthesizer (DDS) that uses advanced technology, coupled with an internal high speed, high performance DAC to form a complete...
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AD9954 on Analog.com

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AD9954 PLL stability issues

		
	
				

			

									
					    SquirrelPCB
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jun 17, 2026 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		            		    
Product Number:  AD9954  

    		        		    		    

		    		    
		    			

			    
Hello,


I am facing stability issues with the AD9954. 
The device is clocked by an external 20MHz clock with multiplier of 20. SyncClk is not used.


Observed is the lock-up of the device, where it stops reacting to SPI commands and does not output signal anymore. 


This happens both with FTW and RAM Mode, but more likely during RAM mode scenario. I have multiple AD9954 on the board and multiple boards and observe similar behaviour on all of them.


When this happens after few minutes to few hours, LOOP_FILTER pin voltage goes to 1.8V and the output stops. Loop Filter configuration is as suggested in the data sheet for 20x multiplicator.
Sometimes a reset can help, somebody power down is the only solution to get the chip back to react to SPI messages.


1.) Observed is a steep increase in lock-up probability with increase in temperature above 55degC


2.) Reducing the clocking to 300MHz helps in stability, but problem persists


3.) Changing PLL loop Filter configuration and charge pump setting does not have a noticable impact.


As the chip otherwise creates the signals as expected, and the SPI communication looks to be correct on oscilloscope, main problem seems to be with the PLL.


At this point I don't know how to debug and improve this anymore. Are there any suggestions how to debug or proceed with this?

			

			
									
		                             
                        

    

                                            
                 ad9954
                
                                                    
                 D/A Converters (DAC)
                
                                                    
                 hardware
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 20, 2026 2:51 AM
            
            
						
			            		
    
		
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    Hi  ,
    

    Apologies for responding to this late. I have been having problems receiving notifications. 
    

    Your AD9954 PLL is losing lock at 400 MHz (20 MHz × 20), worsening with temperature. This points to the PLL operating at or near its stability margin.
     
    Recommended next steps:
     
    1. Reduce multiplier to 16× and use a 25 MHz reference — stays at 400 MHz system clock but with a more stable PLL operating point (higher phase detector frequency = more loop bandwidth margin).
    2. Check AVDD ripple/noise — PLL lock-up at temperature often indicates marginal power supply decoupling. Add additional 100 nF + 10 nF caps close to AVDD pins.
    3. Check reference clock quality — jitter or ringing on the 20 MHz input degrades PLL stability. Ensure clean, well-terminated signal at the REF_CLK pin.
    4. Try lower multiplier as a workaround — you confirmed 300 MHz (15×) helps. Try 18× (360 MHz) to find the maximum stable operating point for your board.
    5. Monitor DAC_RSET pin — if this drifts at temperature, it can affect internal biasing.
    

    All the best,
    

    Jules
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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