Hi:
I am evaluating the AD9106 for an application that requires the following:
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DDS1 outputs a sine wave.
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DDS2 uses a RAM pattern to generate a square wave or pulse that is synchronous with DDS1, at a frequency equal to 1/N of the DDS1 frequency.
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To achieve tight synchronization, the RAM pattern address counter of DDS2 is driven by the MSB of DDS1.
I would like to understand:
a. When WAVE_SEL = 0 in the WAV_CONFIG register, should PRESTORE_SEL be set to 1 or 3?
b. When WAVE_SEL = 0, is the RAM pattern always controlled by START_DELAY and PATTERN_PERIOD?
c. If the answer to (b) is yes, does this mean it is impossible to achieve exact synchronization between the DDS2 RAM pattern and the DDS1 output frequency? (Because DDS1 is not an integer fraction of the sampling clock fs, while PATTERN_PERIOD can only be an integer multiple of 1/fs.)
d. If the answer to (c) is yes, how can the desired application be realized?
Thank you.
Edit Notes
Modify title[edited by: LiuZhenrong at 4:41 AM (GMT -4) on 11 May 2026]