Category: Datasheet/Specs
Product Number: AD9910
I’m designing a PCB using an AD9910 with quite relaxed phase noise constraints.
I’ve studied the theoretical effects of the internal PLL and an external clock I choose and the overall noise and phase noise contribution should be ok.
Looking at the datasheet (POWER SUPPLY PARTITIONING section), however, I have difficulties figuring out how much can I relax the power partitioning. Do you have some quantitative data on it?
The datasheet qualitative approach is too ambiguous for me to make a decision.
Thanks for any insight you can provide.