brown-out damage to AD9102

Hi echem11 ,

Thanks for using AD9102.

Based on your signal chain and the symptoms you described, the failure suggests latch-up or back-powering during a power supply collapse. Please see below for the breakdown:

• What’s likely damaging the AD9102
  • Improper power sequencing or rapid rail collapse triggering latch-up
    • You can refer to Analog Devices AN-932: Power Supply Sequencing and Winning the Battle Against Latchup in CMOS Analog Switches which describe these mechanisms and specifically call out power-up/down sequencing errors and transients as latch-up causes.
  • Back-powering through SPI or clock pins when the DAC is unpowered
  • Output compliance violations at IOUT pins during faults
    • Please see Section 6. Interfacing to the DDS Output for further reference.
  • Large transient currents through shared grounds during shorts.
    • Please refer again to "Winning the Battle Against Latchup in CMOS Analog Switches" for reference.
• How to confirm on the bench
  • Scope power rails and I/O signals during a forced brown-out
  • Check if SPI/clock remain active after DVDD drops
  • Verify IOUT voltages stay within compliance limits
• Safeguards to prevent damage
  • Add powered-off isolation for SPI and clock lines
  • Use supervisors for proper power sequencing and clock enable control.  Follow ADI’s AN‑932 power‑supply sequencing guidance.
  • Implement eFuse or hot-swap protection on supply rails
  • Add series resistors and clamp diodes at DAC outputs
  • Improve decoupling and ground layout to handle transients

Thanks and kind regards,

Alex

Hi Alex,

Thank you for your detailed response, including the safeguards summary.  I have heard of this concept of latch-up, but have not run into this before, so it's very helpful that you confirmed that this is the most likely explanation.  I must confess, this feels like voodoo to me, just because I have not run into this problem before, and I never gave any thought to things like the importance of what order the power rails come up.

I will read your references in detail. 

As far as the SPI bus isolator, I'm getting the idea is that this is basically an electronic switch that connects the SPI lines from the uC to the AD9102 only when the AD9102 has power - so the AD9102 power is basically an "enable" that closes the switch for each line?  So this would prevent back-powering the AD9102 via SPI bus lines (like SCK) in the case that the AD9102 doesn't have enough power to operate, but the uC still can toggle SPI lines?

Hi echem11 ,

Yes, that’s exactly the idea. A powered-off isolation device (or bus switch) acts like an electronic gate for each SPI line. It only connects the microcontroller to the AD9102 when the AD9102’s supply is valid.
This prevents the microcontroller from driving signals into the AD9102 when the DAC is unpowered or in brown-out, which would otherwise forward-bias the ESD diodes and back-power internal circuits.

Typical implementations:

• Analog switches or bus isolators on SCLK, MOSI, CS, and optionally MISO.
• Enable pin tied to AD9102’s DVDD/CLKVDD power-good or a dedicated supervisor.

You can cross reference your circuit to the schematic of the AD9102 Evaluation Board (found in the "Helpful Files" section).

Thanks and kind regards,

Alex

Hi Alex,

Thank you for confirming my understanding of what the power-off isolation switch does.

I looked at the AD9102 eval board schematic, and I see the block labeled level translation that implements the bus isolation during power-off state.

I appreciate your help.