hello,
We are using the EVAL-AD9914.
We are working with Clock = 3000MHz.
The output frequency is in the range of 500-1000MHz.
We tried to work in integer mode and in modulus mode with many different fraction (FTW, A, B) combinations.
While sweeping the output from 500 to 1000MHz we observe some frequencies that come with relatively close and high spurs.
For example:
Fclock = 3000MHz
Fout = 563MHz
Amp = full scale (4095)
We get one spur at 999kHz offset with power of -79dBc and a second spur at 8.012MHz with power of -79dBc (see attached picture).
Our requirement is to get relatively spurs free output with a span of 60MHz around the output.
We have an ability to shift the Clock Frequency and move the spurs out of this span, but we must be able to predict it mathematically.
In the above example we cannot find any mathematical equation that can help us to predict that scenario and calculate the required Fclock shift.
Please advise :
- Is the above example representing the acceptable spurs level according to the datasheet?
- Do you have any mathematical equation that can describe the relationship between the Fclock, Fout and the spur offset from the Fout?
- Do you have any other method to get the DDS output without spurs in a 60MHz span?
thank you
Gil