Category: Datasheet/Specs
Product Number: AD9959
Hello, I am attempting to control the AD9959 Evaluation Board using an external microcontroller via SPI. My goal is to achieve a SYSCLK of 500 MHz (PLL x20 on a 25 MHz Ref_Clk). The primary issue is that the SYNC_CLK signal does not initialize or start running upon initial setup/power-up, despite the Ref_Clk being present (25 MHz). Since I/O Update is synchronous to the SYNC_CLK, its absence is preventing the activation of the PLL settings, causing a deadlock.
What is the precise sequence or required minimal configuration that must be written via SPI before the first I/O Update pulse to guarantee the PLL locks and the SYNC_CLK starts?
