SYNC_CLK Really required for usage of single chip AD9951

Hi Prasanth89 ,

BY default should be 0 which means SYNC_CLK pin is active. However, when activated, the SYNC_CLK pin assumes a static logic 0 state to keep noise generated by the digital circuitry at minimum. However, the synchronization circuitry remains active internally to maintain normal device timing. 

To answer your question, yes, it is required to use AD9951 however, you can disable it so avoid noise generated at minimum. 

All the best,

Jules

Hi Jules.Nikko 

 Thanking you for replying. in hardware point of view can i ground the SYNC_CLK and SYNC_IN as well disable the both in registers. then its working fine or not. please check my hardware connections attached below.

Regards

P Prasanth

Hi Prasanth89 ,

I can't seem to check your schematic as the image is too pixelated. I cannot zoom in. Can you send me a more high-definition image?

All the best,

Jules

Hi Jules.Nikko 

I have attached pdf file for AD9951 please go through once.

Hi Jules.Nikko 

Could you please provide PCB recommandations. PCB LAYERS, PCB Material Type.

in AD9951 Two different grounds are used so how to common both grounds. by using ferrite bead if ferrite bead used then specify the part number for ferrite bead or else any other solution is there to common both AGND and DGND

Regards

P Prasanth