Hello
I have a custom design which uses one AD9958 (with 100MHz LVPECL Oszillator), one AD9510 and two AD9959.
The SYNC_CLK output of the AD9958 (running with PLL x4 or x5, 100Mhz or 125Mhz) is the clock source for a AD9510.
The AD9510 is used as the clock source for two AD9959. The 8 channels of the two AD9959 should run synchronized.
I have also a secondary 100MHz LVPECL Oszillator connected to the AD9510 as second clock source.
First I tested with 500MHz system frequency using a SYNC_CLK of 125MHz with AD9959 PLL x4.
- Frequencies, phases and amplitudes I can program, this is working fine to generate ~30..50MHz.
- The devices can run with Auto Hardware sync (AD9958 as initiator, both AD9959 as targets.)
but this normally not needed, because after power up and stabilization of the AD9959 PLL's
the SYNC_CLK's are running always in phase with currenty an offset of 360ps.
- The IO_Update signal is controlled by a PIC32 MPU. The PIC32 output is connected to a D-FF (D) which is
clocked by the SYNC_OUT of one of the AD9959 to synchronize the IOUpdate Output of the MCU to both
IO_Update inputs of the AD9959. The IO_Update at the AD9959 inputs are also with a timing difference of ~400ps.
- If use the IO_Update of the MCU after SPI parameter changes (or no parameter changes) of the AD9959
the 8 channels of both AD9959 are perfect in phase with the known 360ps offset.
BUT: In one of about 200 IO_Update cycles (not clearly defined, sometimes more "good" updates)
it happens that the 4 channels of one of the AD9959 have suddenly a phase offset of about 90°.
The SYNC_CLK's are not affected in this situation, they are still in phase.
I read in some application notes that the IOUpdate is very critical and must be synchronized (D-FF),
but I did not see any information about the allowed time shift between both AD9959. I think that
for a device running with 2ns clock 400ns of shift should be no problem, but..
What could be the problem ?
