AD5933: Steep rise in phase

Question

Hi all, 
 I'm using the AD5933 eval board in order to test an impedance measurement cell. I use shielded cables (30cm) to connect the cell with the board. The cell behaves like a capacitor. 
 I used the following settings for the measuerements: 
 Rfeedback: 1M Rcal: 1M Start frequency: 3kHz Delta: 220Hz 511 points Settling Time Cycles: 15 Upp Output: 1V Gain: 1 Settling Time: X2 Multipoint Calibration 
 During my measurements i observed steep rises in the phase for which I had no explanation. 
 Because of this I installed a 10p capacitor instead of my measurement cell, but it shows a similar result: 
 
 Do you have got an explanation why the rise in the phase is that steep? 
 
 Thanks in advance!

Snorlax · Accepted Answer

The most likely issue is too much signal that makes the receiving end of the AFE and/or the AD5933 to clip the voltage sine wave at the power supply rails. If you have access to an oscilloscope, the best way to check is to connect it to the RFB pin of the AD5933 ans see if the voltage sine wave there is well-formed, free of clipping or other distortions and whether its baseline is close to Vdd/2 at all frequency steps throughout the sweep. Since you are using evaluation board, you can look at the same voltage at pin 7 of the U1-B (Fig.31, p. 27 of this guide ). As you are sweeping the frequency, the capacitive impedance Z changes in inverse proportion to frequency. This impedance Z and RFB turn U1-B into inverting amplifier with a gain factor of RFB/Z. At low frequencies Z is larger than RFB and gain is lower than 1, but as frequency is increasing Z becomes lower than RFB and when it becomes lower than 0.5*RFB, your 1V p-p excitation voltage is amplified more than 2 times and the U1-B output voltage coming to the AD5933 starts exceeding 2V p-p, and as frequency increases further the U1-B and/or the AD5933 internal input OPAMP start clipping this voltage as it starts exceeding the available dynamic range of the circuits in the signal chain. Further, the AD5933 internal ADC samples distorted sine wave and feeds it to the DFT, which unwittingly crunches the incorrect numbers as if those were coming from the properly digitized proper sine wave, producing the erroneous results. Unfortunately, there is no warning to the user of this happening. So, the strategy of sweeping wide frequency range with frequency-dependent impedance involves anticipating of this effect and changing excitation voltage (and sometimes PGA gain) accordingly. For example, in case of your 10pF load with your settings one could consider sweeping frequency from 3KHz to 30KHz (where Z changes from about 5M to 500k), then programming the excitation voltage of 0.4V and sweeping from 30KHz to 80KHz, then programming 0.2V and sweeping from 80KHz to 160KHz. This could be even more critical as, depending on the design, your cell can have a capacitance considerably higher that 10pF. Depending on how it is connected and the type of the shielded cable. it can easily add 35-45pF in parallel to the cell (those cables can have a capacitance anywhere between 1 and 2pF per cm of length). Perhaps it would make sense to reduce the RFB from 1M to, say, 100k, use calibration resistor of the same 100k and start operation with 2V p-p excitation voltage reducing it later as needed. It is always helpful to watch the changes in the raw Re and Im data as the primary "source of truth": all other values are derived from these two and can either be incorrectly calculated or obscure real behaviour of the chip.)

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AD5933: Steep rise in phase

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