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AD9910 Recommended for New Designs
The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates up to 1 GSPS. The AD9910 employs an advanced...
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AD9910 on Analog.com

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AD9910 Eval software RAM loading errors

		
	
				

			

									
					    tkloyd
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jun 23, 2010 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user experiences inconsistent loading of RAM data files into the AD9910 evaluation software, with occasional correct loads and a fatal error when enabling the multiplier with the OSK Digital Ramp Control window open. The support engineer suggests using a setup file and a 101-word RAM file in Raw Binary format to consistently load and read the RAM data, and advises checking the REFCLK input and PLL multiplier settings to ensure they are within the AD9910's specifications.
                        	    
    
                
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    In my application I want to have a certain profile perform a frequency sweep, so I want to use RAM control.  My problem is that loading my RAM Data File into the RAM using the eval software seems wildly inconsistent, meaning I load my file, then perform the Read RAM to file, and the two files are never identical.
    
 
    I've "gotten lucky" a few times where the file was written into RAM correctly, but haven't been able to identify a process that makes this work all the time.  I've tried in both RAW Hex and RAW Decimal formats, and I've tried data files of various lengths, from 12 addresses to all 1024.
    
 
    Has anyone else had this problem?  Is there any other way to load the RAM?
    
 
    As a sidenote, during my poking around trying to fix this, I've discovered that clicking the 'Enable Multiplier' checkbox on in the Control window while the OSK Digital Ramp Control window is open causes a fatal error for the eval software.
    
 
    Thanks for any help,
    
 
    Thomas
    
			
    
			
									
		                             
                        

    
    
                                            
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                on Dec 12, 2012 5:44 AM
            
            
						
			            		
        
		
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        Hi Sitti
        
 
        Sorry for replaying on this link again, I have started a new discussion yesterday but no one yet replayed so I am asking here in hope of getting any solution.. I am posting my query from that discussion https://ez.analog.com/thread/17455 . 
        
 
        Hi
        
 
        I am using AD9910 evaluation. Before coming to my original problem of chirp generation, as a new user of this evaluation kit I have observed some thing of which I have no explanation. kindly guide me :
        
 
          
  
        • I am providing the external Reference clock to my board, and used PLL multiplier block "without populating loop filter components on Kit" (because I didn't knew at that time) and tried to generate a single tone wave form and I got nothing on output (as it should be because there are no filter component installed) but when I checked the "PFD X Reset" block surprisingly I started to got the output frequencies which are about 1.55 times the desired frequency which I had specified in the GUI (for e.g. 10 MHz appears to be 15.55 and 70 MHz appeared as 108.5 MHz etc..).
          • 
 
        
 
          
        
 
          
  
        1. After reading through different experts comment, for using PLL multiplier there has to be a loop filter..so without connecting loop filter, this type of output is just a coincidence or a functionality of which I have no information?
          2. 
 
        
 
           2. I tried to generate chirp signal using only external reference clock (NO PLL multiplier, clk divider disabled) via DRG and OSK mode with these specification
        
 
                                                                    Ref clk= 80 MHz
        
 
                  sweep 0= 0.001 MHz                                                    sweep 1=     5 MHz
        
 
                  Rising step size= 0.01 MHz                                           Rising step size=  0.01 MHz  
        
 
                  Rising step Interval= 0.003 us                                         Rising step Interval=  0.003 us
        
 
        I specified the lower and upper frequencies for sweep and the rising step size,but I am not able to specify the rising step interval of my own choice. Software is putting some limit. Instead of 0.003us software itself changes it to 0.05 us. Is there any lower limit of rising step interval?
        
 
        Thanks in advance
        
 
        Regards
        
 
        Salman Dinani
        
 
         
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Dec 12, 2012 5:44 AM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi Sitti
          
 
          Sorry for replaying on this link again, I have started a new discussion yesterday but no one yet replayed so I am asking here in hope of getting any solution.. I am posting my query from that discussion https://ez.analog.com/thread/17455 . 
          
 
          Hi
          
 
          I am using AD9910 evaluation. Before coming to my original problem of chirp generation, as a new user of this evaluation kit I have observed some thing of which I have no explanation. kindly guide me :
          
 
            
  
          • I am providing the external Reference clock to my board, and used PLL multiplier block "without populating loop filter components on Kit" (because I didn't knew at that time) and tried to generate a single tone wave form and I got nothing on output (as it should be because there are no filter component installed) but when I checked the "PFD X Reset" block surprisingly I started to got the output frequencies which are about 1.55 times the desired frequency which I had specified in the GUI (for e.g. 10 MHz appears to be 15.55 and 70 MHz appeared as 108.5 MHz etc..).
            • 
 
          
 
            
          
 
            
  
          1. After reading through different experts comment, for using PLL multiplier there has to be a loop filter..so without connecting loop filter, this type of output is just a coincidence or a functionality of which I have no information?
            2. 
 
          
 
             2. I tried to generate chirp signal using only external reference clock (NO PLL multiplier, clk divider disabled) via DRG and OSK mode with these specification
          
 
                                                                      Ref clk= 80 MHz
          
 
                    sweep 0= 0.001 MHz                                                    sweep 1=     5 MHz
          
 
                    Rising step size= 0.01 MHz                                           Rising step size=  0.01 MHz  
          
 
                    Rising step Interval= 0.003 us                                         Rising step Interval=  0.003 us
          
 
          I specified the lower and upper frequencies for sweep and the rising step size,but I am not able to specify the rising step interval of my own choice. Software is putting some limit. Instead of 0.003us software itself changes it to 0.05 us. Is there any lower limit of rising step interval?
          
 
          Thanks in advance
          
 
          Regards
          
 
          Salman Dinani
          
 
           
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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