Post Go back to editing

ADF4350's SPI configration problem

Thread Summary

The user inquires about configuring the ADF4350 using NIOS II SPI in an FPGA. The ADF4350's LE pin functions similarly to the CS pin in SPI, acting as a load signal to latch data into the register. The ADF4350 does not have an SDO (MISO) pin, so only write operations are supported. Wiring the NIOS II SPI signals as described will allow register writes to the ADF4350.
AI Generated Content

hello:

       we want to use FPGA+ADF4350 to generate two high frequency clk(up to 2.4GHz),  ADF4350 can be configured in SPI bus standard.

As we know, there are four signals of SPI, but there only there for ADF4350'SPI.

We want to konw is the LE pin of ADF4350 is the same as cs pin of SPI bus standard?

The NIOS II software core is integrated in altera's FPGA, we can use SPI of NIOS II to config lots of ADI chips(AD9518 AD8322 and so on) with conveniency. Can we config ADF4350 in the same way(NIOS II SPI)?

SPI BUS standard ------------ ADF4350

   SCLK                --------------CLK(PIN1)

   CS                   --------------LE(PIN3)

   SDIO             ----------------DATA(PIN2)

   SDO             ---------------NO PIN

thanks!