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AD9959 Recommended for New Designs
The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This...
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AD9959 on Analog.com

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AD9959: Data valid time

		
	
				

			

									
					    rbe
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 1, 2012 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user inquired about the minimum and maximum data valid time (t_DV) for the SDO data output relative to the falling edge of SCLK in the AD9959 data sheet. The support engineer confirmed that the new data changes after the falling edge of SCLK, within a range of 0 ns to the minimum data valid time, and suggested sampling the data at the falling edge of SCLK for optimal results. The SCLK max rate for read-back is slower compared to writing, but the exact t_DV values were not provided.
                        	    
    
                
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    Hi
    
 
    Unfortunately I do not understand exactly the Timing Specification for serial I/O port in the data sheet.
    
 
    As indicated on page 31 of 44 the SDO data is clocked out on the falling edge of SCLK.
    
 
    The data SDO changes after the falling edge of SCLK after the Data valid time (t DV).
    
 
    This time (t DV) may change over all devices (process variation) and over environment conditions. 
    
 
    So normally there is a specification for the fastest and for the slowest time (t DV).
    
 
    May you give me explicitly the exact values for the fastest and for the slowest data valid time?
    
 
    Thanks 
    
 
    Rolf
    
			
    
			
									
		                             
                        

    
    
                                            
                 44
                
                                                    
                 clock and timing
                
                                                    
                 Clocks & Timers
                
                                                    
                 ad9959
                
                                                    
                 Direct Digital Synthesis (DDS)
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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                on Oct 16, 2012 9:59 AM
            
            
						
			            		
        
		
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        Thanks for your answers.
        
 
        So the the new data changes relative to the falling edge of SCLK somewhere between 0 ns and t DV 
        
 
        (t DV = the minimum data valid time).
        
 
        Or in other words:
        
 
        the time from the falling edge of SCLK to the new data at the output is
        
 
          
  
        • bigger than 0 ns   but
          • 
  
        • shorter than the minimum data valid time
          • 
 
        
 
        So (and that is the most important fact for someone using this device) the falling edge is the optimal point to sample the output data of the AD9959. 
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Oct 16, 2012 9:59 AM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Thanks for your answers.
          
 
          So the the new data changes relative to the falling edge of SCLK somewhere between 0 ns and t DV 
          
 
          (t DV = the minimum data valid time).
          
 
          Or in other words:
          
 
          the time from the falling edge of SCLK to the new data at the output is
          
 
            
  
          • bigger than 0 ns   but
            • 
  
          • shorter than the minimum data valid time
            • 
 
          
 
          So (and that is the most important fact for someone using this device) the falling edge is the optimal point to sample the output data of the AD9959. 
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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