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AD9910 Recommended for New Designs
The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates up to 1 GSPS. The AD9910 employs an advanced...
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AD9910 Ramp rising step interval problem?

		
	
				

			

									
					    salmandinani
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Dec 11, 2012 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user encountered issues with frequency generation and chirp signal parameters on the AD9910 evaluation kit. The final answer explained that the PLL loop filter must be populated for proper PLL operation and provided the formula Δt = 4M/Fsys for the ramp rate, which limits the minimum rising step interval to 0.05 us with an 80 MHz system clock. Accompanying answers clarified that the ADT1-1WT transformer limits the output frequency to 400 kHz and above, and that generating a pulsating chirp signal requires external control beyond the evaluation software.
                        	    
    
                
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    Hi
    
 
    I am using AD9910 evaluation. Before coming to my original problem of chirp generation, as a new user of this evaluation kit I have observed some thing of which I have no explanation. kindly guide me : 
    
 
      
  
    • I am providing the external Reference clock to my board, and used PLL multiplier block "without populating loop filter components on Kit" (because I didn't knew at that time) and tried to generate a single tone wave form and I got nothing on output (as it should be because there are no filter component installed) but when I checked the "PFD X Reset" block surprisingly I started to got the output frequencies which are about 1.55 times the desired frequency which I had specified in the GUI (for e.g. 10 MHz appears to be 15.55 and 70 MHz appeared as 108.5 MHz etc..).
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    1. After reading through different experts comment, for using PLL multiplier there has to be a loop filter..so without connecting loop filter, this type of output is just a coincidence or a functionality of which I have no information?
      2. 
 
    
 
       2. I tried to generate chirp signal using only external reference clock (NO PLL multiplier, clk divider disabled) via DRG and OSK mode with these specification
    
 
                                                                Ref clk= 80 MHz
    
 
              sweep 0= 0.001 MHz                                                                     sweep 1=     5 MHz
    
 
              Rising step size= 0.01 MHz                                                            Rising step size=  0.01 MHz   
    
 
              Rising step Interval= 0.003 us                                                          Rising step Interval=  0.003 us 
    
 
    I specified the lower and upper frequencies for sweep and the rising step size,but I am not able to specify the rising step interval of my own choice. Software is putting some limit. Instead of 0.003us software itself changes it to 0.05 us. Is there any lower limit of rising step interval? 
    
 
    Thanks in advance
    
 
    Regards
    
 
    Salman Dinani 
    
			
    
			
									
		                             
                        

    
    
                                            
                 clock and timing
                
                                                    
                 Clocks & Timers
                
                                                    
                 Direct Digital Synthesis (DDS)
                
                                                    
                 ad9910
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Dec 11, 2012 6:07 PM
            
            
						
			            		
      
		
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      Hi Salman Dinani,
      
 
      I'm sorry for the late response and thank you for using the AD9910.
      
 
      1)Yes, when using the PLL multiplier, the PLL loop filter must be populated. You can use the excel file PLL Loop Filter Tool as provided in this link: AD9910 Evaluation Boards and Kits to help you compute the loop filter component values.
      
 
      2)Based on your setting, your start frequency is 0.001MHz. Are you able to have that frequency? If you are getting your output at J4 (filtered out), kindly take note that the operating frequency of ADT1-1WT is from 0.4MHz to 800MHz.
      
 
      About your rising and falling step interval, the equation used for computing the ramp rate is: 
      
 
      Δt = 4M/Fsys
      
 
      So, if your system clock (Fsys) = 80 MHz, and you want the lowest ramp rate, you have M=1.
      
 
      Δt = (4*1)/80M = 0.05us
      
 
      That is why it automatically sets the value for ramp rate to 0.05us.
      
 
      Thus, the rising/falling step interval is dependent on your system clock.
      
 
      If you change your system clock to 1000MHz, then the lowest ramp rate you will have is:
      
 
      Δt = (4*1)/1000M = 0.004us.
      
 
      That will be your lowest ramp rate because AD9910 is specified to run at maximum of 1000MHz system clock.
      
 
      Hope this helps.
      
 
      Best Regards,
      
 
      Sitti
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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                on Dec 13, 2012 10:32 AM
            
            
						
			            		
        
		
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        Hi 
        
 
        Thanks sitti for your answer. I have verified the formula  Δt = 4M/Fsys and it is indeed providing frequencies accordingly. I have few other queries.
        
 
        1. The lowest correct frequency I am able to get is .01 MHz i.e. 10 KHz..below this waveform is heavily     distorted. Why is it so??
        
 
        2. I want to make a pulsating chirp wave form of pulse width 10 us and pulse repetition frequency (PRF) 1 KHz.
        
 
            I have generated a chirp wave of 3 us using Digital Ramp generator, but now I want to make it pulsating i.e. 
        
 
            I want to turn of my output after 10 us and will turn it on after 1 ms (i.e. PRF of 1 KHz). Is there any option in     software to do that?
        
 
        3. I have read from data sheet that DROVER pin is used to make the ramp zero, so I thought of applying a     square wave to that pin but it appeared to me that DROVER is automatically controlled by software?
        
 
        Kindly suggest me of making a pulsating chirp waveform.
        
 
        Best Regards,
        
 
        Salman Dinani
        
 

        
 

        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Dec 13, 2012 7:30 PM
            
            
						
			            		
        
		
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        Hi Salman Dinani,
        
 
        I will try to answer your queries: 
        
 
        1) The DDSs are guaranteed to have an output frequency of DC up to the Nyquist Frequency (Fsys/2). However, since you are using the AD9910 evaluation board, the output you are reading is being limited by the transformer used in the board. The transformer ADT1-1WT has an operating frequency range of 0.4MHz (i.e. 400kHz) to 800MHz. The 0.01MHz (10kHz) you are reading is maybe due to the margin of the transformer's bandwidth. 
        
 
        2) Unfortunately, using the evaluation software alone won't be able to perform your pulsating chirp signal. What I can think of is to program the AD9910 using an external control.
        
 
        3) The DROVER pin is an output pin. It indicates the status of your DRG. So, if the ramp is at either of the programmed limits, the DROVER pin is logic 1, otherwise, it is logic 0. In a way, it is automatically controlled by the software because whatever is your programmed upper or lower limit, that is when the DROVER pin changes to logic 1.  
        
 
        Hope this helps.
        
 
        Best Regards,
        
 
        Sitti
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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