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AD9914 Recommended for New Designs
The AD9914 is a direct digital synthesizer (DDS) featuring a 12‑bit DAC. The AD9914 uses advanced DDS technology, coupled with an internal high speed...
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AD9914 on Analog.com

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Using SPI (from FPGA) to control AD9914 for single tone output

		
	
				

			

									
					    petelu
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 27, 2013 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is troubleshooting an issue with no output from the AD9914 DDS evaluation board when attempting to generate a single tone using an FPGA. The final answer indicates the thread is closed, suggesting the issue was resolved offline. Key clarifications include checking the jumper settings (P203, P204, P205) to ensure external control is properly configured, and ensuring all control pins, including profile pins, are not floating. The default profile when P205 is disabled is profile 7, which must be addressed for configuration.
                        	    
    
                
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    Hi I have an evaluation card for the AD9914 DDS (AD9914/PCBZ) but wanted the FPGA to control the DDS to generate a simple single tone from one Profile registers. However I did not see any output after setting up the registers. Below are my sequence o commands
    
 
    I set up the SPI sequence of the following:
    
 
    1) Upon power up, issue Reset (Reset_Buf)
    
 
    2) Write to register 0x03 to enable DAC Calibration (bit 24 = '1')
    
 
    3) Write to register 0x03 again to clear DAC Cal (bit 24 ='0')
    
 
    4) Write to register 0x01 to enable Profile Mode Enable
    
 
    5) Write to register 0x0B to set up Profile 0 Frequency tuning word
    
 
    6) Write to register 0x0C to set up Amplitude scale 
    
 
    7) Pulse IOUpdate 
    
 
    Does that sequence seem resonable or am I missing something?
    
			
    
			
									
		                             
                        

    
    
                                            
                 spi
                
                                                    
                 clock and timing
                
                                                    
                 Clocks & Timers
                
                                                    
                 Direct Digital Synthesis (DDS)
                
                                                    
                 ad9914
                
                                        
                                            
                
                
                                
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on May 2, 2013 12:59 PM
            
            
						
			            		
      
		
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      Note, when the jumpers mentioned above are set to disable, the outputs of the ICs on the evaluation board driving the DDS are tri-stated. This to avoid BUS contention from external control. However, all the output nodes of these ICs then need to be tied off or controlled. It sounds like you're controlling reset and IO-UPDATE but other pins must be controlled too instead of floating. For example, down let the EXTPDCTL or SYNC_IO pins float. Also, the profile pins need to be configured to the internal profile register you're pointing to.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on May 2, 2013 12:59 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Note, when the jumpers mentioned above are set to disable, the outputs of the ICs on the evaluation board driving the DDS are tri-stated. This to avoid BUS contention from external control. However, all the output nodes of these ICs then need to be tied off or controlled. It sounds like you're controlling reset and IO-UPDATE but other pins must be controlled too instead of floating. For example, down let the EXTPDCTL or SYNC_IO pins float. Also, the profile pins need to be configured to the internal profile register you're pointing to.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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