Is AD9910 IO_UPDATE line gated by chip select?

Hi David,

You can refer to this circuit note for reference on multiple chip sync on AD9910s: Circuit Note | CN0121 | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers | Analog Devices

DDS cores has I/O buffered register and active registers.

The serial write (SDIO, SCLK, -CS) only writes to the inactive register  (I/O buffer) of the DDS.

The I/O_UPDATE is a different input. A rising edge on I/O_UPDATE initiates a transfer from inactive register to active register. You can refer to page 42 of AD9910 datasheet.

What we recommend, is write first on the I/O buffer, before sending all the register values to the active registers.

Is the IO UPDATE line enabled by chip select?

So, it is better not to enable I/O_UPDATE thru chip select because you need to consider the hold-time and set-up time of I/O_UPDATE with respect to SYNC_CLK.

The recommended setting would be, to have a different control for I/O_UPDATE. You can serially write to all DDSs and then, issue I/O_UPDATE to all DDSs.

Can several AD9910s share a common IO UPDATE line?

Yes you can, as long as your microcontroller GPIO current limit is set to drive all the AD9910 I/O_UPDATE input. The logic 1 current for each AD9910 has max value of 150uA.

IF not, I suggest you use a buffer or CMOS driver before sending the I/O_UPDATE signal to make sure you have enough drive capability. This will also serve as protection, allowing isolation of output/input of the system.

Hope this helps.

-Sittie

Hi Sittie,

Thank you for the reply.

Please accept my apology. I have failed to state my question clearly.

I have two AD9910 chips that need to be controlled by one microcontroller. I am not concerned about synchronizing the two DDS chips.

Sometimes I need to send commands to DDS 1 and other times I need to send commands to DDS 2. I can clearly do this by dedicating a serial port, chip select and IO update line to each DDS. This of course makes them independent and works just fine.

My question is, how many control lines can be shared by the two DDS chips? Certainly each chip needs it's own chip select. However the two chips can share the serial data clock and serial data line. This is possible because these serial communication lines are enabled by chip select. That is to say, the DDS chip ignores these lines unless chip select is asserted.

So my question is, does the DDS also ignore IO Update when chip select is not asserted?

This is what I meant by the word "gated". Sorry for being cryptic.

My concern is this. If the DDS is always responding to rising edges on IO Update even while chip select is not asserted, it will be transferring old data from the buffer registers to the active registers.

In summary, do I need to run a dedicated IO Update line to each DDS?

Again, I do not care a bit about synchronizing the two DDS chips.

Thanks for the load current specs for the IO Update line.

Cheers,

David

The chip select line does not internally gate the IO_UPDATE signal..So, the IO_UPDATE is independent of chip select. However, if a particular DDS does not have the chip select enabled, no new changes can occur, thus multiple IO_UPDATES thereafter would only present the old results every time.