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How to write successfully user data to RAM in AD9957

Hi,

It seems that this issue has already been raised at this forum. Unfortunately, even though I tried to follow exactly the suggested steps I couldn't get the data successfully delivered to the memory in AD9957. In particular, I'm not sure how to organize the sequence of signals during RAM loading. I tried as follows:

1. CS = low

2. Send RAM address (0x16)

3. Send N 32-bit words one after another (with I/O_Update issued after each of them)

4. CS = high

Sometimes, I see that the first bit is changed but all the other are unaffected by the above procedure.

I will appreciate any suggestions.

Bartek

Parents
  • I don't see any impact of the N-divider on the functioning of the whole system in the interpolating DAC mode, although that impact should be expected. Anyway, I have changed CFR3 to 0x123f0142 (N = 33). These settings allow generating single tone at 280 MHz (or any other) successfully, so I hope I don't need to change them. By the way, my PLL operates correctly. I have confirmed that in two ways:

    1. using single tone

    2. reading back the content of several registers (it proofs that my reading algorithm works ok)

    However, when I try to write anything to RAM (e.g. 128 32-bit words), the read from RAM consists of 32-bit words of 0xFFFFFFFF. For technical reasons, I can't copy that data at the moment as I communicate with my DDS chip via STM32 microcontroller.

    There is for sure something wrong with my RAM load procedure, which looks as follows:

    short y = 0x0000;

    short Q = 1;

    spi_send_register(0x16); //send RAM Register address

    for (int k = 0; k < 128; k++)
    {

    y = round(32767*cos(Q*2*3.14159*k/128));

    RAMdata.bits31_16 = y;
    RAMdata.bits15_0 = 0x0000;

    spi_send_register(RAMdata); //send consecutive 32-bit words

    }

    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0

    /CS = 1

Reply
  • I don't see any impact of the N-divider on the functioning of the whole system in the interpolating DAC mode, although that impact should be expected. Anyway, I have changed CFR3 to 0x123f0142 (N = 33). These settings allow generating single tone at 280 MHz (or any other) successfully, so I hope I don't need to change them. By the way, my PLL operates correctly. I have confirmed that in two ways:

    1. using single tone

    2. reading back the content of several registers (it proofs that my reading algorithm works ok)

    However, when I try to write anything to RAM (e.g. 128 32-bit words), the read from RAM consists of 32-bit words of 0xFFFFFFFF. For technical reasons, I can't copy that data at the moment as I communicate with my DDS chip via STM32 microcontroller.

    There is for sure something wrong with my RAM load procedure, which looks as follows:

    short y = 0x0000;

    short Q = 1;

    spi_send_register(0x16); //send RAM Register address

    for (int k = 0; k < 128; k++)
    {

    y = round(32767*cos(Q*2*3.14159*k/128));

    RAMdata.bits31_16 = y;
    RAMdata.bits15_0 = 0x0000;

    spi_send_register(RAMdata); //send consecutive 32-bit words

    }

    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0

    /CS = 1

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