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How to write successfully user data to RAM in AD9957

Hi,

It seems that this issue has already been raised at this forum. Unfortunately, even though I tried to follow exactly the suggested steps I couldn't get the data successfully delivered to the memory in AD9957. In particular, I'm not sure how to organize the sequence of signals during RAM loading. I tried as follows:

1. CS = low

2. Send RAM address (0x16)

3. Send N 32-bit words one after another (with I/O_Update issued after each of them)

4. CS = high

Sometimes, I see that the first bit is changed but all the other are unaffected by the above procedure.

I will appreciate any suggestions.

Bartek

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  • According to your programming sequence, CFR3 = 0x113f0100.

    If so, then I cannot see how the PLL is functioning properly as the last byte indicates the N-divider is set for N=0, which is not a valid value.

    Without first knowing the system clock frequency, I cannot validate the 349MHz output frequency.

    Using the PLL requires some extra work:

    1. Determining the proper loop filter component values
    2. Selecting the correct internal VCO
    3. Selecting the proper charge pump current

    It would be easier if you could use a high frequency generator (~1GHz) at the REF_CLK input, as this would eliminate the nuances associated with the PLL. If you elect to use a generator, be sure the XTAL_SEL (pin 95) is Logic 0 and CFR3[15:8]=0xC0.

    Changing the formula variables or switching from cosine to sine should have no impact on the ability to produce a signal. Something else is going on.

    Can you put the 1024 32b RAM words in a file and post it?

    It would be most helpful if you provide the actual 32b words (hex or binary) as written to RAM. This will allow me to at least validate your RAM data (one less "unknown" to deal with).

    By the way, do you read back and verify the contents of RAM after you've written them?

    It would be helpful to know that you can read back what you've written, as it eliminates another "unknown".

Reply
  • According to your programming sequence, CFR3 = 0x113f0100.

    If so, then I cannot see how the PLL is functioning properly as the last byte indicates the N-divider is set for N=0, which is not a valid value.

    Without first knowing the system clock frequency, I cannot validate the 349MHz output frequency.

    Using the PLL requires some extra work:

    1. Determining the proper loop filter component values
    2. Selecting the correct internal VCO
    3. Selecting the proper charge pump current

    It would be easier if you could use a high frequency generator (~1GHz) at the REF_CLK input, as this would eliminate the nuances associated with the PLL. If you elect to use a generator, be sure the XTAL_SEL (pin 95) is Logic 0 and CFR3[15:8]=0xC0.

    Changing the formula variables or switching from cosine to sine should have no impact on the ability to produce a signal. Something else is going on.

    Can you put the 1024 32b RAM words in a file and post it?

    It would be most helpful if you provide the actual 32b words (hex or binary) as written to RAM. This will allow me to at least validate your RAM data (one less "unknown" to deal with).

    By the way, do you read back and verify the contents of RAM after you've written them?

    It would be helpful to know that you can read back what you've written, as it eliminates another "unknown".

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