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How to write successfully user data to RAM in AD9957

Hi,

It seems that this issue has already been raised at this forum. Unfortunately, even though I tried to follow exactly the suggested steps I couldn't get the data successfully delivered to the memory in AD9957. In particular, I'm not sure how to organize the sequence of signals during RAM loading. I tried as follows:

1. CS = low

2. Send RAM address (0x16)

3. Send N 32-bit words one after another (with I/O_Update issued after each of them)

4. CS = high

Sometimes, I see that the first bit is changed but all the other are unaffected by the above procedure.

I will appreciate any suggestions.

Bartek

Parents
  • What kind of signal source are you applying to the REF_CLK pins?

    The contents of CFR3 indicate that the system clock PLL is enabled. We need to make sure the system clock is set up properly before trying to do anything else.

    Also, I will retract my earlier comment of "contrary to the datasheet" with regard to RAM Enable. The datasheet makes sense, because enabling the RAM automatically puts it in playback mode. When doing RAM read/write operations via SPI, you don't want the RAM controller trying to play back data to the I/Q signal path. Therefore, you should move your RAM write sequence to precede the write operation to CFR1 that enables RAM.

    By the way, the I/O_Update following the RAM write sequence is unnecessary.

    Regarding your RAM data code...

    The method for generating Q cycles of a cosine wave spanning P samples with N-bit quantization is as follows:

    A = [2^(N-1)] - 1

    y(k) = round{A*cos(Q*2*pi*k/P)}   <== k = 0 .. P-1

    The above yields y as a P-element vector of signed integers with a peak value of A. A is chosen so that the quantized cosine wave is symmetric about zero. I think when you cast y as an int in C it is represented in twos-complement form.

    Each 32-bit RAM word constitutes both an I and Q value, with I allocated to the 16 MSBs and  Q allocated to the 16 LSBs. However, because you are using Interpolating DAC mode, only the I values matter. So, the RAM words are the y values left-shifted by 16.

Reply
  • What kind of signal source are you applying to the REF_CLK pins?

    The contents of CFR3 indicate that the system clock PLL is enabled. We need to make sure the system clock is set up properly before trying to do anything else.

    Also, I will retract my earlier comment of "contrary to the datasheet" with regard to RAM Enable. The datasheet makes sense, because enabling the RAM automatically puts it in playback mode. When doing RAM read/write operations via SPI, you don't want the RAM controller trying to play back data to the I/Q signal path. Therefore, you should move your RAM write sequence to precede the write operation to CFR1 that enables RAM.

    By the way, the I/O_Update following the RAM write sequence is unnecessary.

    Regarding your RAM data code...

    The method for generating Q cycles of a cosine wave spanning P samples with N-bit quantization is as follows:

    A = [2^(N-1)] - 1

    y(k) = round{A*cos(Q*2*pi*k/P)}   <== k = 0 .. P-1

    The above yields y as a P-element vector of signed integers with a peak value of A. A is chosen so that the quantized cosine wave is symmetric about zero. I think when you cast y as an int in C it is represented in twos-complement form.

    Each 32-bit RAM word constitutes both an I and Q value, with I allocated to the 16 MSBs and  Q allocated to the 16 LSBs. However, because you are using Interpolating DAC mode, only the I values matter. So, the RAM words are the y values left-shifted by 16.

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