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AD9957 Recommended for New Designs
The AD9957 functions as a universal I/Q modulator and agile upconverter for communications systems where cost, size, power consumption, and dynamic performance...
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How to write successfully user data to RAM in AD9957

		
	
				

			

									
					    bsalski
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Dec 5, 2016 
				
			
			
		

		
		                     
				
        		

		    
		    		    
		    			

			    
Hi,

 
It seems that this issue has already been raised at this forum. Unfortunately, even though I tried to follow exactly the suggested steps I couldn't get the data successfully delivered to the memory in AD9957. In particular, I'm not sure how to organize the sequence of signals during RAM loading. I tried as follows:

 
1. CS = low

 
2. Send RAM address (0x16)

 
3. Send N 32-bit words one after another (with I/O_Update issued after each of them)

 
4. CS = high

 
Sometimes, I see that the first bit is changed but all the other are unaffected by the above procedure.

 
I will appreciate any suggestions.

 
Bartek

			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Dec 6, 2016 3:07 PM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    See my comments below imbedded in a copy of your previous post.
    
 
    1. single tone works ok
    
 
    2. in the interpolating DAC mode, any changes of RAM size affects periodicity of the generated signal but the content is incorrect (noisy) What do you mean by noisy? You should be able to read back from RAM exactly what was written.
    
 
     
    
 
    Let me share with all my sequence hoping you will find some mistakes:
    
 
    General notes regarding SPI transfers...
    
 
    1. You can make CS=1 at the top and CS=0 at the bottom (that is, it is not necessary to toggle CS for each SPI operation.
    
 
    2. It is not necessary to toggle I/O_RESET for each SPI sequence, as you only need an I/O_RESET if the SPI controller gets lost (an unlikely occurrence).
    
 
    /CS = 1
    SCLK = 1
    MASTER_RESET = 1
    MASTER_RESET = 0
    
 
    //CFR1 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x00
    0x01000002
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //CFR2 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x01
    0x00400020
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //CFR3 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x02
    0x113f0100
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //PROFILE0 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x0e
    0x0480000000000000
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //RAM Segment Register 0 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x05
    0x000100030004
    
 
    The RAM Segment 0 settings:
    
 
     Address Step Rate = 1
    
 
    Address End = 0
    
 
    Address Start = 0
    
 
    Mode = Continuous recirculate
    
 
    This implies a RAM address range of 1 (from address 0 to address 0). I'm not 100% certain the RAM controller can handle an address range of 1.
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    RT = 0
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
 
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    
 
    Contrary to the datasheet, I'm fairly certain you need to set the RAM Enble bit prior to reading/writing RAM via the SPI port.
    0x16
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1   <== Do not I/O_Update between write/read operations to/from address 0x16
    I/O_UPDATE = 0
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    0x00
    /CS = 1
    
 
    RT = 0   <== this 1-to-0 transition selects RAM Segment 1
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
 
    //CFR1 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0   <== Not sure if this was intended, but it prevents the subsequent register write from occurring.
    
 
    {Ignore my comment above. It is erroneous. -- edited 8/7/2016}
    0x00
    0x9f000002  <== RAM Enabled, Destination=I/Q path, Mode=Interp. DAC
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    RT = 0   <== this 1-to-0 transition selects RAM Segment 1
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Dec 6, 2016 3:07 PM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    See my comments below imbedded in a copy of your previous post.
    
 
    1. single tone works ok
    
 
    2. in the interpolating DAC mode, any changes of RAM size affects periodicity of the generated signal but the content is incorrect (noisy) What do you mean by noisy? You should be able to read back from RAM exactly what was written.
    
 
     
    
 
    Let me share with all my sequence hoping you will find some mistakes:
    
 
    General notes regarding SPI transfers...
    
 
    1. You can make CS=1 at the top and CS=0 at the bottom (that is, it is not necessary to toggle CS for each SPI operation.
    
 
    2. It is not necessary to toggle I/O_RESET for each SPI sequence, as you only need an I/O_RESET if the SPI controller gets lost (an unlikely occurrence).
    
 
    /CS = 1
    SCLK = 1
    MASTER_RESET = 1
    MASTER_RESET = 0
    
 
    //CFR1 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x00
    0x01000002
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //CFR2 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x01
    0x00400020
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //CFR3 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x02
    0x113f0100
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //PROFILE0 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x0e
    0x0480000000000000
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    //RAM Segment Register 0 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    0x05
    0x000100030004
    
 
    The RAM Segment 0 settings:
    
 
     Address Step Rate = 1
    
 
    Address End = 0
    
 
    Address Start = 0
    
 
    Mode = Continuous recirculate
    
 
    This implies a RAM address range of 1 (from address 0 to address 0). I'm not 100% certain the RAM controller can handle an address range of 1.
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    RT = 0
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
 
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0
    
 
    Contrary to the datasheet, I'm fairly certain you need to set the RAM Enble bit prior to reading/writing RAM via the SPI port.
    0x16
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1   <== Do not I/O_Update between write/read operations to/from address 0x16
    I/O_UPDATE = 0
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    0x00
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    0x00
    /CS = 1
    
 
    RT = 0   <== this 1-to-0 transition selects RAM Segment 1
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
 
    //CFR1 settings:
    I/O_RESET = 1
    I/O_RESET = 0
    /CS = 0   <== Not sure if this was intended, but it prevents the subsequent register write from occurring.
    
 
    {Ignore my comment above. It is erroneous. -- edited 8/7/2016}
    0x00
    0x9f000002  <== RAM Enabled, Destination=I/Q path, Mode=Interp. DAC
    /CS = 1
    I/O_UPDATE = 0
    I/O_UPDATE = 1
    I/O_UPDATE = 0
    
 
    RT = 0   <== this 1-to-0 transition selects RAM Segment 1
    RT = 1   <== this 0-to-1 transition selects RAM Segment 0
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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