AD9910 - Loading the RAM data files without Eval-board

Generally, what you are doing seems reasonable.

A couple of observations:

1) CFR3[15]=0 is the device default setting. However, the default setting enables the divide-by-2 block at the REFCLK input, which means your system clock is operating at 500MHz (rather than the desired 1GHz). To bypass the divider, program CFR3[15]=1.

2) RAM Step Rate=0x000A (10 decimal). With a 1GHz system clock, this yields a RAM address step period of 40ns. So, with 1000 RAM address locations, the entire frequency sweep lasts a mere 4us. Do you have a means to reliably observe such a brief chirp? For debugging purposes, I would recommend making the step rate value very large so that the sweep occurs slowly giving you a better chance of observing what is going on.

Also, try writing the RAM data to Register 0x16 with RAM Enable=1. It has always been unclear to me whether this bit should be set or cleared for loading the RAM. In my opinion, given the RAM controller requires knowledge of the RAM start and end address values in the selected RAM Profile, it makes sense to have RAM Enable=1 so that the profile register is in RAM mode (rather than Single Tone mode).

Actually, now that I think about it, you can easily verify whether the RAM Enable should be set or cleared for proper operation. Write a simple test program to load and then read back (verify) the RAM data. Then, run the test with RAM Enable=0. Repeat the test with RAM Enable=1. The method that produces a valid read back of the data is the one to use.

Generally, what you are doing seems reasonable.

A couple of observations:

1) CFR3[15]=0 is the device default setting. However, the default setting enables the divide-by-2 block at the REFCLK input, which means your system clock is operating at 500MHz (rather than the desired 1GHz). To bypass the divider, program CFR3[15]=1.

2) RAM Step Rate=0x000A (10 decimal). With a 1GHz system clock, this yields a RAM address step period of 40ns. So, with 1000 RAM address locations, the entire frequency sweep lasts a mere 4us. Do you have a means to reliably observe such a brief chirp? For debugging purposes, I would recommend making the step rate value very large so that the sweep occurs slowly giving you a better chance of observing what is going on.

Also, try writing the RAM data to Register 0x16 with RAM Enable=1. It has always been unclear to me whether this bit should be set or cleared for loading the RAM. In my opinion, given the RAM controller requires knowledge of the RAM start and end address values in the selected RAM Profile, it makes sense to have RAM Enable=1 so that the profile register is in RAM mode (rather than Single Tone mode).

Actually, now that I think about it, you can easily verify whether the RAM Enable should be set or cleared for proper operation. Write a simple test program to load and then read back (verify) the RAM data. Then, run the test with RAM Enable=0. Repeat the test with RAM Enable=1. The method that produces a valid read back of the data is the one to use.