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AD9912:Signal drift, the output signal is not stable

Thread Summary

The user experienced frequency instability and drift with the AD9912 DDS when using a 1GHz system clock. The issue was resolved by ensuring the S4 pin was correctly connected and not pulled down. The user also inquired about increasing the output power from DAC_OUT and DAC_OUTB to -2 dBm by adjusting the DAC_RSET resistor to achieve a 1V peak-to-peak voltage swing.
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Hi! I have some probelem when using AD9912. I have an input sysclk of 1GHz(system pll bypassed), and i set the FTW register to a fixed number, but i got a signal whose fequency is not fixed. In theory, the output shouldn't be drifting, are there some issues i failed to notice? Thanks for help!