AD9912:Signal drift, the output signal is not stable

Yes, the output frequency of a DDS is proportional to the system clock frequency (1GHz, in your case). The stability of the output frequency is identical to the stability of the system clock frequency. If sysclk is stable, then the output will be stable.

With the PLL bypassed we can rule out the possibility of an improperly configured PLL.

Are you using an AD9912 Evaluation Board or a custom design? How are you measuring the frequency?

I have messured the input system clock, and it is very stable, a sine wave of 1GHz. I am using on a custom design and measure the output signal with Spectrum Analyzer. I don't konw whether i set the correct value to disable the internal PLL, are there any suggestions on checking the register value? Thanks for answering.

Be aware that the four status pins (S1-S4) establish the initial device configuration at power-up. It is possible, that at power up, the device is NOT bypassing the PLL (see Power Up section of the data sheet -- Table 8 in particular). Make sure the S4 pin has a pull-up resistor, which results in the PLL being bypassed at power up.

Also, for applications that bypass the PLL, the data sheet recommends connecting a 1kΩ resistor from the LOOP FILTER pin (pin 31) to GND.

Be aware that the four status pins (S1-S4) establish the initial device configuration at power-up. It is possible, that at power up, the device is NOT bypassing the PLL (see Power Up section of the data sheet -- Table 8 in particular). Make sure the S4 pin has a pull-up resistor, which results in the PLL being bypassed at power up.

Also, for applications that bypass the PLL, the data sheet recommends connecting a 1kΩ resistor from the LOOP FILTER pin (pin 31) to GND.

It confuses me. I have computed the value of FTW, it ought to be like 20MHz according to the FTW and fs(1GHz), but i got 22MHz. At the same time, the frequency is not stable, drifting from 21.5 MHz to 22.5 MHz.I have double checked the S4 pin and pin 31 you mentioned, it's rignt. Sad...

If the PLL is, indeed, bypassed, the output frequency must be absolutely stable (at least to the extent that the system clock input frequency is stable).

Read register 0x0010. Bit D4 should be Logic 1 (PLL power down). If not, program Bit D4=1.

If Bit D4 reads back as Logic 1, but the output is not completely stable, then you may have a defective part.

Thanks very much. I made a mistake and connect the S4 pin to a pull-down resistor.Now it is stable.By the way, i want to ask another question. Can i raise the power of the output signal from DAC_OUT and DAC_OUTB.I can only get -2 dBm sine wave, ike raising the vp-p to 1V. Can i achieve this by changing the resistor conneted to DAC_RSET?

The voltage compliance of the DAC output pins is ±500mV about AVSS. This means that, at most, the peak-to-peak voltage swing must be ≤1V. A signal level greater than this will require an output amplifier.