Direct Digital Synthesis (DDS)

Q&A

by suyogchoudhari1 Direct Digital Synthesis (DDS)

Latest 7 days ago by suyogchoudhari1

28 1 0

Not Answered
AD9910 DRG Mode – Frequency Sweep with Multiple Exclusion Bands and No Dwell Time 0
Not Answered

Hello, We are using the AD9910 DDS and plan to implement a frequency sweep using the Digital Ramp Generator (DRG) . Our application requires a continuous sweep from 20 MHz to 100 MHz , but within this sweep there are several frequency bands where...

D/A Converters (DAC) software

28 1 0
by JuanPabloRodriguez Direct Digital Synthesis (DDS)

Latest 7 days ago by Snorlax
48 1 0
Not Answered
I need to connect a Heltec v3 LoRa Wifi Module to the EVAL-AD5933EBZ Rev-C by I2C bus but can't find where to connect it 0
Not Answered

Hi, I am builfing a biosensing sensor and I want to use the EVAL-AD533EBZ module connected to a Heltec v3 LoRa Wifi module to do sweeps every 10 minutes and send the data to a database, first need to wire the Heltec Module to the Eval Module by I2C...

hardware i2c eval-ad5933ebz sda Direct Digital Synthesis (DDS) scl EVAL-AD5933EBZ Rev-C Show More

48 1 0
by LiuZhenrong Direct Digital Synthesis (DDS)

Latest 13 days ago by AlexAtienza
167 3 1
Not Answered
AD9106:How to use the RAM pattern 0
Not Answered

Hi: I am evaluating the AD9106 for an application that requires the following: DDS1 outputs a sine wave. DDS2 uses a RAM pattern to generate a square wave or pulse that is synchronous with DDS1, at a frequency equal to 1/N of the DDS1 frequency...

Datasheet/Specs D/A Converters (DAC) ad9106

167 3 1
by Ajithkumar Sundar Direct Digital Synthesis (DDS)

Latest 19 days ago by Ajithkumar Sundar

249 2 0

Not Answered
Output Power level requirement 0
Not Answered

Dear Team, Kindly provide the output power level details of the AD9914 for the below inputs: 1. Fs - 3GHz 2. Fout - 1.1GHz and 1.35GHz As per below attached image, is there any power level variation in out desired output.

D/A Converters (DAC) hardware ad9914

249 2 0
by Sarmad Direct Digital Synthesis (DDS)

Started 1 month ago

94 0 0

Not Answered
AD9910 Noisy Output 0
Not Answered

I have a custom board with AD9910, with it's differential output connected to a balun and single-ended output connected to output SMA connector. I have measured it's output using spectrum analyzer while in frequency sweep mode using DRG, from 100 MHz...

ad9910 eval kit AD9910 EVAL D/A Converters (DAC) hardware ad9910 output ad9910 dds ad9910 Show More

94 0 0
by Divakaran Direct Digital Synthesis (DDS)

Latest 2 months ago by Jules.Nikko
339 3 0
Not Answered
OPEN and RESERVED register definitions 0
Not Answered

Hi ADI Engineer Zone We are in the process of fault-finding an issue that uses AD9914. We have written the register CFR3, Control Function Register 3 - 0x02, its default value of 0x0000191C. Note here the bit positions 7, 23 and 24 to 31are defined...

Datasheet/Specs D/A Converters (DAC) hardware Clock ICs clock and timing ad9914 Show More

339 3 0
by Selina Direct Digital Synthesis (DDS)

Started 2 months ago

138 0 0

Not Answered
AD9958 Ref Clk detection fails 0
Not Answered

Hello, I am trying to operate a AD9958/59 Evaluation board Z Rev C (ad9958/PCBZ) with the ad9958/59 evaluation software. It is connected to the PC via usb, cr1 is lighting green, cr2 is blinking red. VCC_USB and DVDD_10 are powered with 3.3 V, gnd is...

AD9958 eval board D/A Converters (DAC) hardware AD9958/AD9959 Evaluation Software (Rev. 2.0.0) ad9958 Show More

138 0 0
by Shiphi Direct Digital Synthesis (DDS)

Started 2 months ago

130 0 0

Not Answered
Reading EVAL-AD5933EBZ register using python 0
Not Answered

Using PyUSB and libusbk 3.1.0.0 I was trying to read the register 0x9F. The below are the snippets of the code. def __init__(self, vid=0x0456, pid=0xB203): self.dev = usb.core.find(idVendor=vid, idProduct=pid) def read_reg(self, reg): try: #...

software A/D and D/A Converter Combinations EVAL-AD5933EB registers python ad5933 eval-ad5933 Show More

130 0 0
by KTeng Direct Digital Synthesis (DDS)

Started 2 months ago

93 0 0

Not Answered
AD9952 Loop_Filter Connection 0
Not Answered

HI, Please advise on AD9952 LOOP_FILTER (PIN12) connection. if I am using an external differential REF_CLK source(400MHz), do I leave the LOOP_FILTER pin open/NC　or GND to AG? Toru

Datasheet/Specs D/A Converters (DAC) ad9952

93 0 0
by dbdevices Direct Digital Synthesis (DDS)

Latest 3 months ago by dbdevices

337 3 0

Answered
AD9102 Datasheet: Apparent discrepancy between Figure 33 and BGDR description of Table 19 +1
Answered

Hello, The description of the BGDR field given in Table 19 seems to indicate that: A BGDR value of 0x1F should correspond to an on-chip reference voltage of 0.84 V. A BGDR value of 0x20 should correspond to an on-chip reference voltage of 1.24...

Datasheet/Specs ad9102 clock and timing Direct Digital Synthesis (DDS)

337 3 0
by VishnuPrakash Direct Digital Synthesis (DDS)

Latest 3 months ago by Jules.Nikko
297 2 0
Not Answered
Regards of Issue in DRTCL. 0
Not Answered

Hello sir... I am using AD9914 DDS for Rising sweep generation. In that i am facing issue in DRTCL pin. I am using arduino uno for control the DRCTL (P102-DRCTL-BUF) by external trigger. Output of the Arduino uno is 5v, so connected one Buck convertor...

hardware clock and timing Direct Digital Synthesis (DDS) ad9914

297 2 0
by molun Direct Digital Synthesis (DDS)

Started 3 months ago

115 0 0

Not Answered
Parallel Mode 0
Not Answered

HI, I am using an AD9854 module, and its pins include RST (MASTER RESET), A0-A5, D7-D0, FSK, OSK, four 3.3V, two GND, WR, and RD. It only supports parallel mode. I use Verilog language for programming and driving, and the set program clock is 1 MHz...

software clock and timing ad9854 AD9854Parallel operation Direct Digital Synthesis (DDS) Show More

115 0 0
by RolfOle Direct Digital Synthesis (DDS)

Latest 3 months ago by Jules.Nikko
254 1 0
Not Answered
Wideband chirp generation 0
Not Answered

Hi, I want to confirm the chirp capabilities of the AD9914 for FMCW radar applications. Assuming we are using the AD9914 evaluation board. Let’s say we use a 125 MHz reference clock and the internal PLL with a x20 multiplier to get a 2.5 GHz system...

hardware clock and timing Direct Digital Synthesis (DDS) ad9914

254 1 0
by dbdevices Direct Digital Synthesis (DDS)

Latest 3 months ago by AlexAtienza
349 3 0
Answered
AD9102: Hold last pattern sample after pattern period executed +1
Answered

Hello, We are evaluating the AD9102 using development board AD9102-ARDZ-EBZ and associated controller board EVAL-SDP-CK1Z. We have successfully used the ACE software to generate an SRAM-stored waveform with the desired shape; however, we have been unable...

Datasheet/Specs AD9102 EVAL board ad9102 dac output clock and timing Direct Digital Synthesis (DDS) Show More

349 3 0
by LeandroMarceddu Direct Digital Synthesis (DDS)

Started 3 months ago

149 0 0

Not Answered
CN0349 copy 0
Not Answered

Hello, We're trying to get a conductivity measurement working on our main boards. We've especially taken an interest in the CN0349 because of it's limited requirement of space. In the attachments we've copied your schematic to our main kicad file...

hardware clock and timing ad5934 Direct Digital Synthesis (DDS) cn0349 Show More

149 0 0

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Q&A

Not Answered
AD9910 DRG Mode – Frequency Sweep with Multiple Exclusion Bands and No Dwell Time 0
Not Answered

Not Answered
I need to connect a Heltec v3 LoRa Wifi Module to the EVAL-AD5933EBZ Rev-C by I2C bus but can't find where to connect it 0
Not Answered

Not Answered
AD9106:How to use the RAM pattern 0
Not Answered

Not Answered
Output Power level requirement 0
Not Answered

Not Answered
AD9910 Noisy Output 0
Not Answered

Not Answered
OPEN and RESERVED register definitions 0
Not Answered

Not Answered
AD9958 Ref Clk detection fails 0
Not Answered

Not Answered
Reading EVAL-AD5933EBZ register using python 0
Not Answered

Not Answered
AD9952 Loop_Filter Connection 0
Not Answered

Answered
AD9102 Datasheet: Apparent discrepancy between Figure 33 and BGDR description of Table 19 +1
Answered

Not Answered
Regards of Issue in DRTCL. 0
Not Answered

Not Answered
Parallel Mode 0
Not Answered

Not Answered
Wideband chirp generation 0
Not Answered

Answered
AD9102: Hold last pattern sample after pattern period executed +1
Answered

Not Answered
CN0349 copy 0
Not Answered

Q&A

Not Answered AD9910 DRG Mode – Frequency Sweep with Multiple Exclusion Bands and No Dwell Time 0 Not Answered

Not Answered I need to connect a Heltec v3 LoRa Wifi Module to the EVAL-AD5933EBZ Rev-C by I2C bus but can't find where to connect it 0 Not Answered

Not Answered AD9106:How to use the RAM pattern 0 Not Answered

Not Answered Output Power level requirement 0 Not Answered

Not Answered AD9910 Noisy Output 0 Not Answered

Not Answered OPEN and RESERVED register definitions 0 Not Answered

Not Answered AD9958 Ref Clk detection fails 0 Not Answered

Not Answered Reading EVAL-AD5933EBZ register using python 0 Not Answered

Not Answered AD9952 Loop_Filter Connection 0 Not Answered

Answered AD9102 Datasheet: Apparent discrepancy between Figure 33 and BGDR description of Table 19 +1 Answered

Not Answered Regards of Issue in DRTCL. 0 Not Answered

Not Answered Parallel Mode 0 Not Answered

Not Answered Wideband chirp generation 0 Not Answered

Answered AD9102: Hold last pattern sample after pattern period executed +1 Answered

Not Answered CN0349 copy 0 Not Answered

Not Answered
AD9910 DRG Mode – Frequency Sweep with Multiple Exclusion Bands and No Dwell Time 0
Not Answered

Not Answered
I need to connect a Heltec v3 LoRa Wifi Module to the EVAL-AD5933EBZ Rev-C by I2C bus but can't find where to connect it 0
Not Answered

Not Answered
AD9106:How to use the RAM pattern 0
Not Answered

Not Answered
Output Power level requirement 0
Not Answered

Not Answered
AD9910 Noisy Output 0
Not Answered

Not Answered
OPEN and RESERVED register definitions 0
Not Answered

Not Answered
AD9958 Ref Clk detection fails 0
Not Answered

Not Answered
Reading EVAL-AD5933EBZ register using python 0
Not Answered

Not Answered
AD9952 Loop_Filter Connection 0
Not Answered

Answered
AD9102 Datasheet: Apparent discrepancy between Figure 33 and BGDR description of Table 19 +1
Answered

Not Answered
Regards of Issue in DRTCL. 0
Not Answered

Not Answered
Parallel Mode 0
Not Answered

Not Answered
Wideband chirp generation 0
Not Answered

Answered
AD9102: Hold last pattern sample after pattern period executed +1
Answered

Not Answered
CN0349 copy 0
Not Answered