In the High-Z mode the two analog input channels of the ADALM1000 provide a 1 mega ohm input resistance but in parallel there is nearly 400 pF of capacitance as we saw in this earlier blog entry. While working on this example lab activity on a CMOS output transconductance amplifier ( OTA ) I found that I was unable to probe the output of the second stage, at the drains of PMOS M4 and NMOS M5 in figure 2 of the Lab, without the amplifier becoming very unstable. Note the screen shot, figure 1, of the scope display when channel B was connected to this node. The channel A green curve is the input of the amplifier which is configured with an inverting gain of 6.8. The channel B orange curve shows the oscillation.
Figure 1, Oscillation with channel B connected to second stage
Not being able to observe the waveform on this internal node of the amplifier was becoming very irritating. So I pulled out a circuit I had used for another project that needed a very low capacitance input.
In figure 2 we see the schematic for one channel of an N-JFET input buffer source follower. The design in its most simple form uses one N channel JFET, Q1, and an NPN current mirror, Q2 and Q3, as the current to drive the source of Q1.
Figure 2, FET source follower input buffer
N-channel JFETs are depletion mode devices and when used as source followers can provide nearly zero input to output voltage offset if biased at the proper ID current. The choice of N-JFET to use could be from a number of possibilities as long as the source load current is adjusted to be equal to the ID value where VGS is equal to zero. The combination of the fixed and adjustable resistors are used to set the drain current and thus the input to output voltage offset. I had three device types on hand to try. The 2SK117, 2SK193 and 2N4338. The magic ID current for the 2SK117 was around 2 mA and for the 2SK193 also 2 mA. The 2N4338 zero VGS ID was much lower at around 280 uA. Another perhaps more widely available FET might be the Fairchild J112 and J113 devices with zero-gate voltage drain currents of 5 mA and 2 mA.
The gate input capacitance for the 2N4338 and 2SK193 are both listed as 5 pF with the gate capacitance for the 2SK117 somewhat higher at 13 pF. Any of these values are much smaller than the nearly 400 pF of the ALM1000 input structure.
The FET buffer can be powered directly from the fixed +5 V supply on the ALM1000 analog connector which will limit the allowed range of analog input voltages to be somewhat less than the 0 to +5 V supported by the analog inputs because of the headroom needed by the source follower and the current source. Two NMOS transistors such as 2N7000 could be used in place of the NPN (2N3904) devices in the current mirror. MOS current sources should have slightly lower headroom requirements than the BJT current source. To provide the extra supply voltage provision is made to insert 1.5 V batteries below ground and above the 5 V supply. For my prototype mock-up I used L1131 button batteries. Current draw is very low for the buffers and the batteries could last for up to 100 hours of use.
Now with the very high input resistance and very low input capacitance of the FET buffer we can observe the sensitive internal node of the OTA without disturbing the frequency stability of the amplifier. As we can now see in the scope screen shot in figure 3. Again the green curve is the input signal. The dark orange curve is the output of the amplifier and the lighter orange curve is the output of the second stage of the amplifier. We can now see this node as we should, quickly jumping as the NPN and PNP halves of the push-pull output stage turn on and off.
Figure 3. No Oscillation with FET buffer connected to second stage
A second important benefit of the significantly lower capacitance is the ability to use just resistors for input attenuators rather than needing frequency response compensating capacitors as in this note on the ALM1000 analog inputs. To test this out I used two 510 KΩ resistors as a 2X attenuator as shown in figure 4:
Figure 4 Resistor only input voltage divider
Figure 5 is a screen shot showing channel A generating a 2 KHz 0 to 5 V square wave, green trace, and the attenuated and buffered signal on channel B, orange trace. Note the vertical scale of channel B goes from -2.5 V to +7.5 V. We see that the insertion of the 510 KΩ resistor in series with the gate of the FET without a frequency compensation capacitor has not affected the rise/fall time of the signal enough to be visible within the bandwidth of the ALM1000.
Figure 5, FET buffer with input resistor attenuator
Figure 6 is a rendering of what the top of the 0.8” X 2.0” PCB with two FET buffers will look like. Design files for this board are included in the zip file attached to this blog.
Figure 6, FET probe PCB top layer
On the top left the 6/8 pins of the ANALOG1 connector pass through to the 1X8 pin second analog connector (ANALOG2). The buffer outputs at the source of the FET can be connected to either the CHA/B pin or the optional input only AIN/BIN pins through jumpers JPA and JPB. The 5 pin PROBE header connector contains the channel A and B FET inputs along with two ground pins. The center pin is connected to the fixed +2.5 V power supply to provide a mid swing reference for any external resistor divider that might be used ahead of the buffer to allow larger input voltage ranges as in figure 4. On the right side of the board are places for the two offset adjustment resistors.
The plus and minus button batteries can be inserted into the two 2X2 0.1” header sockets using the technique shown in figure 7. The spacing between diagonal pins in the 2X2 header is just about right to fit the thickness of the battery. Shorting jumpers can be inserted to operate from just the fixed +5 V supply.
Figure 7 Easy way to connect a 1.5 V or 3 V button battery to PCB.
In conclusion we now have a way to effectively buffer the adverse effects of the large input capacitance of the ALM1000 analog inputs.
As always I welcome comments and suggestions from the user community out there.