Part of register setting: Reg 01h<14> = 1 Reg 1Ah<9:0> = 40h ; Reg 1Ah<11:10> = 1:1 ; Reg 1Ah<13:12> = 1:0; Reg 1Ah<19:14> = 0h ; Reg 1Bh<3:0> = 2h ; Accroding to data sheet( if I dont understand anything wrong), the pin 33(LD_SDO) would always output the lock detect signal in this setting. However, when I have gotten the locked…(Show moreShow less)
About HMC930A. Is the gain stated in the datasheet the effective gain or should I subtract from it the losses due to return loss? For example, if I am inserting a power of 10dBm to the HMC930A, is the output about 20dBm or would it be less due to the return loss?
Hi, can anyone help with HMC8205BF10 please? the marking is "H8205B" it should be "H205B" if we look at the datasheet (page 14) http://www.analog.com/media/en/technical-documentation/data-sheets/HMC8205BF10.pdf Is it mistake in datasheet? Thank You for your answers. Best regards Paolo
Hi, When I have a looked at the datasheet, in page 32 there is a land pattern which was used in the eval board of AD5375. But in page 35 OUTLINE DIMENSIONS is different comparing with the page 32. If you check it you will see e-pad dim of CP-24-7 is about 100mil but in land pattern used in eval board is 82mil. It is 18mil smaller than the…(Show moreShow less)
We have got HMC8191. When we apply LO signal to 23 pin we have no response in the IF outputs. So we tried to send a 12 Hz 15 dBm signal to various inputs. When we apply LO signal to 24 pin we have some response in the IF outputs. But when we smoothly reduce amplitude of signal at 24 pin, amplitude of output signal (pin 10 and 12) decreases…(Show moreShow less)
Hello, I am utilizing HMC6300/6301 connected to Tx and Rx to transmit/receive the 16-QAM data, however, the iio-oscilloscope I use to display signal can only show 4-QAM (like attached picture). Whatever how I changed the type of QAM (like 8QAM, 32QAM), it can only display the 4-QAM signal. By the way, the iio-device is FPGA with AD-FMCDAQ2.…(Show moreShow less)
Looking at table 5.8 of the HMC PLL operating guide (http://www.analog.com/media/en/technical-documentation/user-guides/pll_operating_guide_rf_vcos.pdf ), the user is instructed to program values to various bits of register 6 that differ from the power on defaults without any explanation. e.g. bit 10 defaults to 0, but has the description "Program…(Show moreShow less)
Follow the datasheet recommendations to guarantee operation for all operating conditions. In this example Reg 6 controls the delta sigma modulator (DSM) clock delay. We found the DSM would only work reliably with PFD frequencies > 50 MHz if the clock was delayed (Reg 6=1). All registers are set to a best guess default during design…