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arodgers234
I'm somewhat confused as to what the clock rate is for the 9371. I have a profile generated to run my evaluation board at 100 MHz, however, the profile lists a clock rate of over 200 MHz. My understanding is that this is oversampled so that some additional processing can be done in the Ad9371.   My question is what this means for the PL logic.… (Show more)
in FPGA Reference Designs
popo
Dear Sir,   Does FMCOMMS3 EVM can support MYC-C7Z020(MYC-C7Z020 CPU Module (industrial grade)  ) CPU Module Board?   The MYC-C7Z020 Schematic i here(MYD-C7Z010/20 Development BoardMYD-C7Z010/20 Development Board | Xilinx Zynq-7010, 7020 ARM Board-Welcome to MYIR ).
in FPGA Reference Designs
justinklchan
Is there a reference Vivado project for how to use the DAC on the FMCDAQ2 with KC705 board?   I'm aware the Wiki contains the HDL files to compile IP blocks and the abstract diagram for how components go together.   But I'm looking for a concrete reference project that shows  a) the HDL and block diagram for connecting the components together… (Show more)
in FPGA Reference Designs
justinklchan
I'm trying to build the HDL files for the FMCDAQ2 on the KC705 board here: https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/kcu105    When I make that directory I get these errors: error copying "daq2_kc705.runs/impl_1/system_top.sysdef": no such file or directory     while executing "file copy -force… (Show more)
in FPGA Reference Designs
ccruztorre
I am using the AD9467 with the interposer card and the Xilinx ML605 and I want to save such a big data set with a ML605. I need to have a DMA in my system. I have the analog project running using a core DMA 5.0 but it is not posible to capture up to 80000 samples. Analog developers (csoml) have the same issue  where It is not possible to capture a… (Show more)
in FPGA Reference Designs
ccruztorre
Dear all, I am working  with the LM605 xilinx, the AD9467 Evaluation Board and the FMC interposer. I have followed the documentation that you provided form the analog devices wiki: https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9467 I uploaded the bit file to the FPGA and I have checked a sinusoidal signal using chipscope busplot to… (Show more)
in FPGA Reference Designs
CodeWarrior
Hi all,   I have a question about the AD9371 IP block as written by ADI.   For a standard implementation of the AD9371 chip, 4 JESD lanes are needed. Why are they organized in pairs for the 9371 reference design? In other words, why is there a separate lane pair producing 64 data bits for the adc_rx_data data port, and another 64 bits for… (Show more)
in FPGA Reference Designs
anki
Hi, I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated.  When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id.   I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is… (Show more)
in FPGA Reference Designs
vecad
I tried using the SDSoC platform generation files here for HDL branch 2016 R2.   Xilinx SDSoc Targeting Example [Analog Devices Wiki]  1)I skipped this step, since the HDL branch 2016 R2 should be updated for these changes.....or I could be wrong.   Update the HDL design to Vivado 2015.2 by running the sdsoc_platform/update_hdl.tcl script.… (Show more)
in FPGA Reference Designs
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