Skip navigation
Announcement 1 EngineerZone will be READ ONLY August 22-28. Click Show Details for more.
Announcement:EngineerZone will be READ ONLY August 22-28. Click Show Details for more.
Log in to follow, share, and participate in this community.

Recent Activity

DSPdesigner
Hello, I am looking at AD reference designs for Xilinx FPGA.   Xilinx claims support for JESD204b over GTP for in its IP core.  However, all the AD JESD204b interfacing examples given are for higher-end devices with GTX transceivers.      Is it possible to use AD9371 with a Xilinx device with a GTP transceiver?   Is there an AD reference… (Show more)
in FPGA Reference Designs
sivaram_crl
We're facing problems of reference clock is creating IMD's with the TX LO freq. If we generate TX LO at 4GHz with Ref. Clock of 40MHz, we are getting 4GHz signal along with 4GHz+40MHz & 4GHz-40MHz. we can't use these frequencies in my band and because of this we're losing system bandwidth. Please suggest a method remove these IMD products. Thanks… (Show more)
in FPGA Reference Designs
ruhen
I would like to interface the AD9172 evaluation board with the Xilinx ZCU102 development board. Are there any Xilinx example projects for the AD9172? From my understanding there is only a pre-programmed microSD card for a KCU-105 platform and not any full Xilinx HDL projects available. I would like to verify my current setup for the correct usage… (Show more)
in FPGA Reference Designs
sivaram_crl
we want to do Frequency hopping at >1000hops/s using AD9364 in FDD mode with 16/32 frequencies. But its having only 8 profiles and only one SPI for both TX freq & Rx freq configuration. How to change Tx&Rx LO independently and simultaneously ? Total RF freq settling should be below 80usec.
in FPGA Reference Designs
Nooj
Hi,   I am currently trying implement an LFM Generator onto a Zedboard with the FMCOMMS3-EBZ with the Linux OS installed.  However, I am not using the GUI and would like to do things from the terminal.   Currently, I am wondering where in the block design I should connect my LFM Generator.  It has an output that provides the digital values of… (Show more)
in FPGA Reference Designs
drewsdsu
Hello,   We are trying to create a design that incorporates both the reference design for the 9371 and a modem that will source data from a SFP port. We have figured out that the reason our Ethernet on the SFP is no longer working is because when we launch the zynq, the device tree changes the default clock of the si570 from 156.25 MHz to… (Show more)
in FPGA Reference Designs
hmen
Hi Analog Devices HDL designers, I am setting up a design where I want to use the axi_dmac component. I use a fifo based input and want to set that datawidth to 384 bits. My AXI memory master output width will be 128 bits, so technically spoken this should not be an issue. I am using the Altera tooling and in order to instantiate my desired FIFO… (Show more)
in FPGA Reference Designs
murali_4i2i
Hi, We are working on One-DAC-Tx only with custom modulator using ADRV-9371. We managed to run on ZC706 headless project with Vivado/SDK 2017.4.1 In TES we configured for 2-lane-Tx. The configuration works with the headless, i.e we see the right spectrum. However we see activity on all 4 lanes from the JESD204b core to the xcvr-phy. Also if we… (Show more)
in FPGA Reference Designs
NilsMinor
Hi,   I am using only one ADC AD9234 channel which requires 5 Gbits /S lane rate. When build my system I got an error in implementation because my design is based on daq2 zc706 template.      I think I need to change a config in my build tcl script, but how?   here is my script in the moment, is something else missing?   Is it also correct… (Show more)
in FPGA Reference Designs
NilsMinor
Hi,   while trying to generate a custom design I get the following error message:   For 1 Channel of the AD9234 in 1 GS mode, I need a data rate of 5.0 Gb/S. Where is this set up? How can I configure the data rate?   Thanks - Nils
in FPGA Reference Designs
Load more items