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chinni
Hello,   I am using zc702 and AD9361 for data transmission. I have made my own HLS IP for modulation. I removed the DMAs from the bare metal design and added FIFO in place of DMA. FIFO interfaces with AD9361.So my final blockdesign has this flow   TX IP -> FIFO -> bit slicer for generating I,Q -> AD9361   I have probed the signals using ILAs in… (Show more)
in FPGA Reference Designs
cerasic
Hi Istvan, Rejeesh and Lars,   First of all, I want to mention you that our  system based on fmcdaq2 hdl (R2017_R1 and No-OS dev branch from August 2017, is working even if it is not stable, it works in one configuration ADC (300 MSPS) and DAC (300 MSPS). I have  checked  FMCDAQ2 without our design, all possible sampling frequencies for DAC and… (Show more)
in FPGA Reference Designs
quandang
Hi, I would like to use ADI AXI_JESD204_RX at JESD204B Link Receive Peripheral [Analog Devices Wiki] for FMCJESDADC1 board. Which HDL and no-OS/linux branch should I use? Thank you.
in FPGA Reference Designs
chris@covariantcorp.com
I just received my ADRV1CRR-FMC and ADRV9361 SOM.  No useful documentation came with the boards.  Where is a getting started guide?
in FPGA Reference Designs
s.kannan
I'm using picozed sdr1x1 SOM with ad9364 in it. I tested data streaming through LIBIIO with a fmcomms4 data streaming simulink model provided by ADI. It's working fine but one third of the time it keeps on loading and got struck in the middle(like at 8%), I kept my simulation time as 50sec. Is it common or is there any problem in my setup? Do I… (Show more)
in FPGA Reference Designs
s.kannan
I'm using picozed sdr1x1 with ad9364 and I tried the fmcomms2_3 data streaming through libiio with ad9364.cfg file. I'm not getting the right waveform at the output. I also copied the Matlab code with modification and I and Q waveforms.   clear; clc; s = iio_sys_obj_matlab; % Constructor s.ip_address = '192.168.10.211'; s.dev_name = 'ad9364';… (Show more)
in FPGA Reference Designs
sherryi
I want to run Serial Rapid IO example on Zynq 7030 using Xilinx SDK. I imported an example named xsrio_dam_loopback_example. I edited its variable MEM_ADDR #define MEM_ADDR   XPAR_PS7_RAM_0_S_AXI_BASEADDR It crashes when program execution reaches XSrio_CfgInitialize() function, the CPU does not halt when I run it in Debug mode in… (Show more)
in FPGA Reference Designs
yanjiesh
Dear all,   I updated vivado to the version of 2016.2  several months ago.  I downloaded a zip file of hdl_master for AD9361 on ZED board of AD-FMCOMMS3-EBZ.  The relevant web information is attached as a PNG file as follows.   I decompressed the zip file into one of disk partitions as F:/hdlmaster. When I ran the tcl file in… (Show more)
in FPGA Reference Designs
Jiwon.Lee
Hi,   I'm checking the operation of AD-FMCADC3-EBZ with ZC706 FPGA board. SW : Vivado 2015.4 and hdl_2016_r1 / no-OS_2016_R1_sdk When I use the latest MASTER with vivado 2016.2, The resource of "AD9625_GT_BASEADDR" in no-OS cource is not assigned, So this caused SDK error. After checking,  found GT_IP is changed to different one at the latest… (Show more)
in FPGA Reference Designs
jsusong
I am using the axi_i2s_adi (dev branch) IP block in a Zynq+ Vivado 2017.2 design targeted for P/N xczu2eg-sbva484-1L-i and it is failing timing.  See below.  Can you help?   Paths failing timing. Active Constraints for the I2S IP block   AXI_I2S IP Configuration Constraint file   Schematic showing one of the data paths that is failing.… (Show more)
in FPGA Reference Designs
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