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Hi,   I am trying to understand the clk scheme for the ad9361 and the IP cores i nthe ref design. I made a figure from what i understand so far for the TX path. clk1 is the clk for the interface as well as ad9361 core and fifo_out. clk2 is the clk for TX FIR filter, clk3 is the HB1 filter clk and so on. i assumed x2 interpolation in all the… (Show more)
in FPGA Reference Designs
Hello, I would like to test the PPS receiver, which has been implemented in the HDL Rerefence designs (hdl_2017_r1) ( ). I use fmcomms2 and ZC706. I would like to used external signals form generator and i found some information in post… (Show more)
in FPGA Reference Designs
Does the Quartus 17.0 AD9371 Arria10 project require external memory connected to the PL? I see there is mention of external PL memory here: hdl/a10soc_plddr4_assign.tcl at hdl_2018_r1 · analogdevicesinc/hdl · GitHub    and it seems that this file gets included in the a10 SoC make-file hdl/Makefile at hdl_2018_r1 · analogdevicesinc/hdl · GitHub   … (Show more)
in FPGA Reference Designs
Someone asked by email:   After building an SD card image and boot-up the Arria10 & AD9371 system there are issues with IIO Oscilloscope. Here are the stats below:   QSYS 17.0 Project:   AD9371 Arria10 Project (\hdl\projects\adrv9371x\a10soc) - ADI HDL Repo tag: hdl_2017_r1 Altera-Linux Branch:… (Show more)
in FPGA Reference Designs
can we connect pmod ad2 to differential pmod host ports JC1 , JD1 and JE1?
in FPGA Reference Designs
Hi All,             Hope all are doing fine.    I have downloaded AD9371 HDL Reference Design from ADRV9371 HDL Reference Design [Analog Devices Wiki]   created and testing the project on ZC706  can I use the same files for creating the project for ZCU102? otherwise can i get the design files for creating AD9371 for ZCU102.   Waiting for your… (Show more)
in FPGA Reference Designs
We designed a signal processing board based on zynq and multiple AD9361s. Several of the 9361s can output normal single-frequency test signals, but the signal-to-noise ratio of several other 9361 output signals is very low. The output signal is a wide peak centered on the local oscillator signal. What is strange is that when the pin constraint on… (Show more)
in FPGA Reference Designs
I have purchase one ad7606 module. Is it possible for you to send the vhdl code for adc ad7606. I am familiar with vhdl code. I am new in vhdl as well as fpga.
in FPGA Reference Designs
I am designing a custom board that utilizes the AD9371 transceiver. The JESD204B bus is connected to an Artix 7 fpga. The Artix 7 is utilized to transmit/receive the ADC and DAC samples to/from our CPU via the PCIe gen2 x4 bus. I want to use the AXI_9371 HDL code to connect between the JESD204B interface and PCIe interface. Do you have a document… (Show more)
in FPGA Reference Designs
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