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ccruztorre
I am building and generating programming files for AD9467 FMC to port ZC796. I have used separately the adapted zed and kc705 project folder (modifying the makefile, tcl files, etc) to port ZC706,. I am using the correct version of vivado 2016.2. I have followed all the steps that analog provided in order to get a right compilation under… (Show more)
in FPGA Reference Designs
Aban
Hi   We have a picozed-sdr-som board with 3 AD9361 connected to it(one  of AD9361 is in the board itself). The  linux Image (from analog devices) running and I am able to stream data to one AD9361 via ad9361_iiostream.c application(we modified the example program) , and oscilloscope application.   In the FPGA we added our own module… (Show more)
in FPGA Reference Designs
cswanson
Would it be possible to use the Analog Devices FMCDAQ2 board on either of the development boards? Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit  Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit  Thanks, Craig
in FPGA Reference Designs
David_Zhang
AD9371 and ZC706 operate in NO-OS, I know that adc_capture() can be used to obtain the digital value in Rx's ADC, and   the digtal value seems to be stored in the address ADC_DDR_BASEADDR (0x800000) , now I want to write the digital   value into Tx' DAC to send the data which is the same as the received data. so my dac function is:  … (Show more)
in FPGA Reference Designs
anki
Hi, I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated.  When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id.   I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is… (Show more)
in FPGA Reference Designs
ffrank
Dear all, I am using the 2016_R1 stable releases of 'hdl' and 'no-OS' for my KC705 board (rev 1.1) combined with an AD-FMCOMMS1-EBZ (rev C). When using the GUI mode of Vivado 2015.4.2, the synthesis is successful, but the implementation stage fails because of not met timing constraints (negative slacks). However when compiling the HDL project with… (Show more)
in FPGA Reference Designs
StefanoG
Hi, From the hdl-2016-r2 project, receive on micro (no-OS) the samples resulting from the radio IPCORE FPGA module. I use a zedboard with the AD9361 sdr module. The samples obtained from the radio, have two component "I" and "Q". What is the physical correspondence of this two component, represents a voltage? what is the unit in this case?… (Show more)
in FPGA Reference Designs
SoerenS
Hi,   I am trying to create a custom HDL tx design for the FMCOMMS 3 or FMCOMMS 5. (I have both on a zc706) I got the MathWorks tools (master branch) working with Matlab 2016b and Vivado 2015.2. My own design is synthesised, but when I opened the design in Vivado, I noticed some timing problems.   By trying to debug, I saw, that some… (Show more)
in FPGA Reference Designs
ccruztorre
I am using the AD9467 with the interposer card and the Xilinx ML605 and I want to save such a big data set with a ML605. I need to have a DMA in my system. I have the analog project running using a core DMA 5.0 but it is not posible to capture up to 80000 samples. Analog developers (csoml) have the same issue  where It is not possible to capture a… (Show more)
in FPGA Reference Designs
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