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Announcement 1 January, 2018 Revisions to ADSP-214xx Anomaly Lists
Announcement:January, 2018 Revisions to ADSP-214xx Anomaly Lists
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I'm testing ADSP-21584 on a custom board. On my custom board I have an FPGA connected through SMC B0, all pins exept ARDY are connected. In my CrossCore 2.8.0 project, 1. the pinmux includes all the used pins for SMC B0. 2. Functions from the FPGA are made available through a pointer to the SMC B0 memory space. 3. Upon startup I configure the… (Show more)
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Hi ADI's   In relation to the question below ADSP-21489 SHARC SPI slave booting   The customer has successfully booted the slave, but no sound is output when the parameter data is downloaded   EVB LED indicates normal status. After downloading the ldr file: LED1, LED2 on - successful boot After parameter download: LED3, LED4 on - successful… (Show more)
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And again I have to seek the help of this forum.   I'm trying to load my finished project onto the SPI parallel flash of my ADSP 21469 EZ-Kit. I successfully created a ldr file, and am triyng now to upload it onto my device with the CLDP.   But when I try to upload it I get the following error message:   C:\Analog Devices\CrossCore Embedded… (Show more)
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What is the best way to interface 2 ADAR7251 chips to an ADSP-21573 so as to allow the maximum sample rate of 1.8 MS/s?
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Hello,        We are still evaluating SHARC Audio EZ-Extender, everything works fine and AD1939 output data with 3ms delay. However if use SRC(Sample Rate Converter), the delay turns to be 15ms.  I check the time sequence of SRC, it's seems below 1us in total.  Can you help to suggest what's the problem of this phenomenon. Thank you.    
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Hi,   I working on it since two days without any success, so I'm looking for your help. Here is my setup : - 8 I2S stereo inputs - 4 I2S stereo outputs - 21489 Sharc DSP I have external buffer to share the BCLK LRCLK to all the devices. I use the example : "adsp-21489-CCES" in CCES 2.7.0 At the beginning, I change the DAI port inputs to… (Show more)
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I tried launching ADSP - 21489 slave for one month but please advise because LDR download will not be done normally. The development environment connects EZKIT (ADSP - 21489) and STM MUC and uses EZKIT (ADSP - 21489) as SLAVE by using it as the SPI master of the MCU. (SPI does not use DMA, LDR used is ss_app_sh489.ldr.) 1. When using SIGMA STUDIO… (Show more)
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Hi,   I want to receive 8ch serial data  from  other dsp  in TDM8 mode  , and use adsp-21489 transmitter  it to dac in I2S.     how to config  the clock?      Master DSP : MCK=12.288MHz                          BCK=12.288MHz (TDM8)                         LRCK=48KHz DCA   :  MCK=12.288MHz              BCK=3.072MHz              LRCK=48KHz  
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My product's manufacturing engineer reports that the IDCODE returned by all four of the ADSP-21469 chips in the JTAG scan chain are returning a value that is different from the expected value from the BSDL file.   Example failure message from the JTAG tester is below. The data is the same for the other 3 SHARCs in the chain. IDCODE for Device… (Show more)
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I'm studying DSP21489, i'd like to use DSP21489 as spi slave mode, communicate with external master mode, where can i find Spi slave mode sample code for DSP21489?
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