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dbSv
Hi, I need some help using the 4 ASRCs on a 21488 SHARC in TDM mode. The topic is to convert an external/incomming TDM8 stream to the internal sample rate of the DSP. On the output side of the ASRC the data should also be packed into a TDM8 stream. The ASRC output should go into one of the SPORTs. The external TDM8 stream is connected by three… (Show more)
in SHARC Processors
AndreySidelnikov
Hello. We are going to test the ADSP-21060 processors. For this, a test firmware is developed which must be loaded into the internal memory of the processor without using VisualDSP. Also we can not use EEPROM on the test card. Tell me how you can solve this problem. Thank you in advance.
in SHARC Processors
jb@hme
The ADSP-21479 Processor Hardware Reference Manual Figure 15-1 "PCG Block Diagram" on page 15-6 shows that the PCG CLK can be inverted (see attached), but I can’t seem to find how to do that described anywhere in the manual. I don't even understand how the inverter placed in parallel with the CLKDIV block is supposed to work for CLKDIV > 1.  Is it… (Show more)
in SHARC Processors
battularamanareddy0@gnail.com
HI all Previously i posted this question but  stil i am not  getting reply from anyone to this question  So please reply as soon as possible    Reg:boot kernel customization in adsp 21062 I have single flash in that to load two .ldr filles regarding that i have faced lmany problems i.e 1.first ldr working fine with customized kernel in… (Show more)
in SHARC Processors
battularamanareddy0@gnail.com
HI all Reg:boot kernel customization in adsp 21062 I have single flash in that to load two .ldr filles regarding that i have faced lmany problems i.e 1.first ldr working fine with customized kernel in sector 0 of flash memory. 2.second  ldr  not working  with default kernel in sector 1 of flash memory(each sector has 1MB memory) for… (Show more)
in SHARC Processors
toani
Hello, I have the following hardware: ADZS-21479-EZLITE Revs DSP 0.2 BOM 1.5 PCB 0.1 with (JTAG Debugger) ADZS-SADA2-BRD DSP 0.2 BOM 1.5 PCB 1.0 ans software: SigmaStudio 3.14.0 and SigmaStudio for Sharc PROD 2.2.0 I have set the DIP switches and Jumpers in the board as indicated in Sigmastudio_for_SHARC_Users_Guide.pdf Table 3,… (Show more)
in SHARC Processors
caoleiwe
Hi everyone,   I am a novice of DSP software development. Recently, I have been having a knowledge of details of SDRAM test of ADSP-21489 EZ-Board of "Power-On-Self-Test" project in the CCES IDE. I am confused with the interrupt settings in the SDRAM test. The below source code come from the "sdram_test.c" file in the "Power-On-Self-Test"… (Show more)
in SHARC Processors
tchadwick@kvh.com
If I set a breakpoint in one of the DSP cores, when I try to debug I get the error message "Failed to set breakpoint at C:\Users\tchadwick\cces\2.8.0\testCore1_Core1\src\testCore1_Core1.c [line: 26] because there is no debug line info.".  I checked the settings and it says that it should be generating debug information (-g option to the… (Show more)
in SHARC Processors
MOUNIKAMADURI
Hi,   ADSP-21469 EZBRD has external Memory DDR2 and flash Memories are available.If we upload any code into board from Cross Core Embedded Studio ,where the data will store either internal memory or external memory (that to DDR2 or Flash).
in SHARC Processors
Rever_Point_212
Hello   We will not use GigE, CAN, external DDR memory.   In order to suppress the current consumption, I want to stop the clock of the unused function block with the CDU_CFG register.   The functional block which carried out the clock stop will not carry out current consumption?   Best Regards
in SHARC Processors
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