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I want to know if a there is a current Link port DMA transfer (or a series of chained transfers) pending before a start a new DMA transfer.     Do I poll the DMACH_IRPT, the EXTTXFR_DONE, or the LPBS?   After I have started a Link port DMA transfer, what do I poll to know that the transfer is complete?   On previous SHARCs I would do the… (Show more)
in SHARC Processors
Ladies Gentlemen,   Please let me ask: One of ADZS-SC589-EZLITE features is 4Gb DDR3 Memory. Stands Gb for gigabyte or for gigabit?   With regards and friendship Georges Theodosiou
in SHARC Processors
hi,     I run the program about block based talk through example adsp21369. I have two questions.First,I build the project and click the run, the program is running.At this time, I can hear the music played.But when I press to Halt, the music is still playing. WHY?  Second,how to modfy block_A/B/C,thus we can get the modified output signal.… (Show more)
in SHARC Processors
Guys, I am working on designing of a test board which involves both FPGA(Xilinx- Kintex 7) and DSP(Tiger Sharc) based signal processing. Now the end user wants to access the DSP processor programming options/ boot configuration through the host PC itself. As I went through the datasheets of these devices I got the idea that I'll have to use PPLP… (Show more)
in Other ADI Processors
I have been chasing down an intermittent problem (Host comms via SPI stops working) with our 21469 framework. It seems to be related to interrupts, but post-mortem debugging has not proved very fruitful so far.    What I did discover is that the illegal condition interrupt was disabled, but an illegal condition was being latched. After enabling… (Show more)
in SHARC Processors
Hej all,   i have a general question about memory access of two components. I use the Sharc 21489. What happens if SPORT DMA wants to write data into internal RAM while the Core wants to read/write data into int.RAM? How is this situation managed?   Best regards     Waleri
in SHARC Processors
Good day Group, I have a board containing a ADSP-21161 SHARC On the board are >  Flash mem for the SHARC FW as well as SDRAM The board contains a legacy JTAG (2x7 pin) interface. I wish to read the FW on the flash via the JTAG interface Which equipment and Software do I require to do this? Can anybody help me with information.   Thank you… (Show more)
in SHARC Processors
Hello,   I've setup a quick test issuing non-chained DMA controlled SPI transfer on an ADSP-21469 Ezboard. The code repeatedly sends a small buffer over the SPIB interface and I've verified this is working fine. I'd like to trigger a DMA complete ISR but it's not firing. I'm using VisualDSP 5.1.2 and I've verified global interrupts are… (Show more)
in SHARC Processors
Hi all   We have an embedded system with a SHARC ADSP-21161 processor with three additional SDRAM in use. The program that is running on the DSP was programmed years ago and I ported it now to VisualDSP++ 5.1. It consists of several parts whereby some parts can be debugged without any problems. However, some parts of the software can not be… (Show more)
in SHARC Processors
Hello,   I'm designing custom systems with ADSP-21478 and BF-592 processors, and I'd like to boot my software from SPI Flash, utilising the VDSP++ Flash Programmer utility. I have successfully done so using the M25P16 parts that are used in the EZ-kits with the flash drivers provided.   Unfortunately it looks like these parts are being phased… (Show more)
in SHARC Processors
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