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topcatnew
Hi I am using the Sharc ADSP21364 with the latest development tool release. I have created a small simple library function called rocket() and have compiled/mapped it into the ldf file. In addition, I have added a preprocessor path to the .h file and a linker search directory path to the .dlb file.   Everything compiles correctly but it fails to… (Show more)
in Other ADI Processors
skottfelt
Hi all   I am using an ADSP-218x as a sequencer for a CCD. Normal readout works perfectly well, and I can also perform a process called 'pocket pumping' (where charge is moved back and fourth between the pixels) of the serial register with a single value. However, I want to change that value for every 5 lines I read out and I cannot get that to… (Show more)
in Other ADI Processors
sgk125
Hi..   I want to communicate between FPGA(Virtex 5)  and ADSP TS201S uing LinkPorts. I found in the memory map of TS201S,there is space dedicated for external memory,internal memory and host space. So if data is being written from FPGA ,through link ports , where should I write that data ?? what is the dedcated space allocated to it?  … (Show more)
in Other ADI Processors
santhanakrishnan
.   I am using 2 ADSP TS201S Processors in my board. I am facing one issue with the link port communication. The link port communication (Only L2) is not happening in ambient temperature. Above 40 to 45°C this communication is happening. I dont know why it is behaving like this. During debugging process we have found the following things.   As i… (Show more)
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rbedinfr
Hello, I am currently studying a bit of the TS-201S processor and I need to understand some of its conventions, such as parameter passing and stack frame construction. When doing the same for other processor brands, I usually looked for the processor programming manual and its "EABI" document, but I was not able to find such a document for the… (Show more)
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mzar.piap
Hi, Can you recommend me #MCU which can interface via #paraller bus (32b wide) with #AD9914 #AD9915 to achive update rate about 40-50MHz? Regards Mikolaj
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mandan
Guys, I am working on designing of a test board which involves both FPGA(Xilinx- Kintex 7) and DSP(Tiger Sharc) based signal processing. Now the end user wants to access the DSP processor programming options/ boot configuration through the host PC itself. As I went through the datasheets of these devices I got the idea that I'll have to use PPLP… (Show more)
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HelenBeh
Hi,    My customer is now facing component degrade issue on their board and need some information about the component reflow profile for ADDI7004. They need the information to study the root cause based on process perspective.   I have requested the datasheet as attached but it seems that they are still unable to find any recommended reflow… (Show more)
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gkoeck
Hi, the data retention for ADuCM 3027 is given typical 10 years. At what temperature ? 85 °C ?   If my app. has only 40 °C, then I can estimate 8 times higher data retention ?   thanks     Gerd
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