• no output signal for LTC2247

    Hi there,   I am using LTC2247 ADC to convert RF analog signal to digital. I have seen the differential input signals on the corresponding pins but there is no signal on the output pins. There might be two possi...
    last modified by YONGfzh
  • AD9694 disparity errors

    Good Morning   I have developed a design that use the Xilinx FPGA ultrascale “XCKU040-FFVA1156” that interface the ADC (AD9694) by using 4 lines JESD. The JESD line rate is > 4 Gbps. The FPGA ...
    last modified by mauriziob
  • Source Code to use ADS7-V2EBZ as an acquisition card

    Hi,  Can you provide C or C++ source code to interface the ADS7-V2EBZ to a computer via USB, so that it may be used as a high speed acquisition card? Specifically, can the evaluation board record trac...
    last modified by yonisher
  • LTC2312-12 Rising edge timing of CONV & SCK

    Hello,   According to the datasheet of LTC2312-12, it is recommended to hold SCK static low or high during tconv. Are there any problems if the rising edge of CONV and the rising edge of SCK is same timing? &#...
    last modified by AkiraO
  • Modifying AD9208 FPGA for ACE

    I am currently working with the Ads7-v2ebz and AD9208-3000ebz for a unique evaluation. I have modified the FPGA image that is on the analog website (https://wiki.analog.com/_media/resources/eval/ads7-v2ebz_13052_revc_...
    last modified by jsaylor
  • ADA2200 - Circuit Example Suggests 125kHz Demod Operation?

    The context for this question is as a high frequency response LVDT Signal Conditioner. I was looking at the ADA2200 datasheet when I came across this passage in applications information: ADA Datasheet pg17 F...
    last modified by JeffreyGage
  • Crosstalk about AD9653

      Dear Sir/Madam,          I am designing a NMR Signal Acquisition Board. What it does is receiving the analog signal modulated at 63.8MHz, and then converted into ...
    last modified by CCloris11
  • LTC2123 bad output data

    Trying to work with LTC2123. We are using JESD204B Subclass 0. Test patterns like K28.5, K28.7, D21.5, Lane Alignment Sequence, Modified RPAT Pattern are work fine. But normal data is terrible. To test LTC2123 we appl...
    created by enclis
  • AD6688 Spur at 2x the output sample rate

    To Whom it May Concern,    I am running the AD6688 at a sample rate of 3GSPS. The NCO is set to convert 1GHz to DC and the decimation factor is 6. On the output spectrum I see a component at DC (1 GHz befor...
    created by Sh1
  • Loading the ADS7v2 with new FPGA

    Hello,   I've download the AD9689_ADS7v2.zip, extracted the Vivado 2015.2 project, I have a valid JESD204 license, and built a bitstream. At this point I am not sure how to correctly load the FPGA. I've tried us...
    last modified by jsaylor
  • How should I properly terminate an unused input on the HMCAD1511?

    I'm only using input one for testing and would like to use Analog's recommended method to terminate the unused inputs.   Thanks, Aleksa
    created by aleksab
  • Controlling sampling frequency of wideband digitizer, e.g. AD9208 or AD9213

    I am interested in using the AD9208 as a wideband digitizer to subsample RF signals, and I like that the input bandwidth for this device is 9 GHz. However, I wish to have control over the sampling frequency (Fs). In t...
    last modified by Dohmana
  • Sampling rate & input BW for AD high-speed ADCs in ~10 years time?

    Am looking into future receiver architectures. Having an idea of approximate values in ~10 years time for parameters such as sampling rate and input BW (based on past trends) would be very useful. Please can you ...
    last modified by nickr
  • AD9208 BW verses Sample Rate

    Hello,    I am looking at using the AD9208 in a SDR application. If the datasheet states "direct sampling wide bandwidth analog signals of upto 5 GHz" but also specifies "-3dB BW of 9GHz", is the 5 GHz spec...
    last modified by WN2A
  • AD9467 Readback problem

    Hi, we are using AD9467 in our design. I am trying to readback chipid just to verify the spi interface. To readback reg 0x01 I am sending the x"8001" data over sdio line. Expected data 0x50 should be seen on sdi...
    last modified by sumala
  • AD7175 register read glitch

    I've been experimenting with an AD7175-8 and I've encountered a problem regarding register writting/reading.  I'm setting up a register with a certain HEX value, yet when reading it back (to verify that the writi...
    last modified by alincp
  • ADS7-v2 EVM FMC connector supply issue?

    Hi, I have a ADS7-v2 EVM and AD9208 EVM boards. Up to now, I have used ACE application to implement ADC data capturing. However, from this point, I want to create my own embedded design into FPGA. When starting, I rec...
    created by aliBugra
  • LTC2312-12 CONV pin pull-up/down

    Hello,   Can we add 1k ohms or 10k ohms pull-up or pull-down resistor to CONV pin? Are there any problems to LTC2312-12 in that case?   Best regards, Akira
    last modified by AkiraO
  • Does the AD9680 chip have design tools to help designers automatically generate data needed for register configuration?

    AD9680芯片是否有设计工具,帮助设计师自动生成寄存器配置所需的数据,类似于TI公司的WEBENCH® Designer。 Does the AD9680 chip have design tools to help designers automatically generate data needed for register configuration, similar to TI's WEBENCH Des...
    last modified by wanch3307@163.com
  • AD9208 configuration difficulties

    Hi,   Our company is currently developing a high-end system based on the AD9172 and AD9208. To speed up the design, we decided to bought your dev boards for each component and also an FPGA board. I’m bus...
    last modified by LCr