Skip navigation
Log in to follow, share, and participate in this community.

Recent Activity

YONGfzh
Hi there,   I am using LTC2247 ADC to convert RF analog signal to digital. I have seen the differential input signals on the corresponding pins but there is no signal on the output pins. There might be two possiblities:  1. I did not programmed the chip correctly. 2. The chip is not working correctly.   For the first one, I have tested the… (Show more)
in High-Speed ADCs
mauriziob
Good Morning   I have developed a design that use the Xilinx FPGA ultrascale “XCKU040-FFVA1156” that interface the ADC (AD9694) by using 4 lines JESD. The JESD line rate is > 4 Gbps. The FPGA design is implemented using VIVADO 2018.1 and the Xilinx IP JESD204 PHY Version 4.0 I have the following situation: If the analog signal input to the ADC is… (Show more)
in High-Speed ADCs
yonisher
Hi,  Can you provide C or C++ source code to interface the ADS7-V2EBZ to a computer via USB, so that it may be used as a high speed acquisition card? Specifically, can the evaluation board record traces using an asynchronous hardware trigger, and the traces be transferred to a MATLAB application at high speed (several hundred traces a second at… (Show more)
in High-Speed ADCs
AkiraO
Hello,   According to the datasheet of LTC2312-12, it is recommended to hold SCK static low or high during tconv. Are there any problems if the rising edge of CONV and the rising edge of SCK is same timing?   Best Regards, Akira
in High-Speed ADCs
jsaylor
I am currently working with the Ads7-v2ebz and AD9208-3000ebz for a unique evaluation. I have modified the FPGA image that is on the analog website (https://wiki.analog.com/_media/resources/eval/ads7-v2ebz_13052_revc_design_files.zip) and would like to have this loaded on the FPGA from the ACE software sutie rather the manually with a JTAG… (Show more)
in High-Speed ADCs
JeffreyGage
The context for this question is as a high frequency response LVDT Signal Conditioner. I was looking at the ADA2200 datasheet when I came across this passage in applications information: ADA Datasheet pg17 From what I see here it suggests that the ADA2200 can be run using a 1MHz clock and can output demod at 125 kHz.   Question 1: Doesn't… (Show more)
in High-Speed ADCs
CCloris11
  Dear Sir/Madam,          I am designing a NMR Signal Acquisition Board. What it does is receiving the analog signal modulated at 63.8MHz, and then converted into digital signal using AD9653. And then the digital signal enters the FPGA for downsampling, downconversion, Cascaded Integrator–Comb (CIC) decimation filtering, etc. After processed… (Show more)
in High-Speed ADCs
enclis
Trying to work with LTC2123. We are using JESD204B Subclass 0. Test patterns like K28.5, K28.7, D21.5, Lane Alignment Sequence, Modified RPAT Pattern are work fine. But normal data is terrible. To test LTC2123 we applied triangular wave to the input, but it looks like ADC has only 4 bits in the whole range. Time domain diagram on image bellow.… (Show more)
in High-Speed ADCs
Sh1
To Whom it May Concern,    I am running the AD6688 at a sample rate of 3GSPS. The NCO is set to convert 1GHz to DC and the decimation factor is 6. On the output spectrum I see a component at DC (1 GHz before down conversion) at -83 dBFS. What I have found is that by adjusting the clock phase (0x0109), fine delay (0x0112), and super fine delay… (Show more)
in High-Speed ADCs
jsaylor
Hello,   I've download the AD9689_ADS7v2.zip, extracted the Vivado 2015.2 project, I have a valid JESD204 license, and built a bitstream. At this point I am not sure how to correctly load the FPGA. I've tried using the JTAG connector to program the FPGA with the Vivado output fpga_dig_top.bit file but the ACE tool produces errors and can't… (Show more)
in High-Speed ADCs
Load more items