HI, I am looking for a clock synthetizer able to output 100MHz, 125MHz and 156.25MHz with PECL outputs. I will use a quartz or oscillator as reference input. Have you a product which can be used in this configuration ? Thanks and Regards,
Hello Zanzibar, We have four solutions: 1. The AD9578 2. The AD9558, AD9559, and AD9554-1. This are DPLL based jitter cleaning PLLs but also work as synthesizers. You might consider these if you want to ultimately have your clocks locked to a reference in your system instead of having it free-running. -Paul Kern
Hi, My customer is using AD9516 with the clock buffer of TI as shown below(refer to attached datasheet). She said that if 10MHz input of clock buffer was connected directly to REFIN of AD9516, there was no problem and when she checked clock performance on output of clock buffer, there was no problem also. But she had a problem that when…(Show moreShow less)
Hi all, My customer has used AD9516-1 reference input in the following conditions. - REFIN : Single-ended LVCMOS, AC-Coupled, 10MHz square wave Recently, she found out the reference input conditions for 10MHz on the datasheet as below. Does she have to remove the AC-Coupled capacitor ? Could you please provide the best reference input…(Show moreShow less)
Dear JH shin, There are two ways to input the CMOS clock, and either is fine: 1. If she AC-couples the signal, she should bypass the complimentary input to ground. If operated in that mode, the input receiver should be in differential mode. One advantage to this mode is that it's possible to impedance match the input. It's true that the…
We are considering the ADF4355-3 for use as a LO source and would appreciate clarification of the VRF supply requirements. The datasheet states VRF must be the same value as AVDD, which in turn must be the same as DVDD. However the datasheet also recommends that different regulators are used for VRF and DVDD. If we were to use one regulator…(Show moreShow less)
If you share the VRF and DVDD regulators, then integer boundary spurs can degrade by ~10 dB. Also, ensure your regulator can provide the required current. If these are ok, then you can proceed. For the sequencing, ensure you don't violate any rules in Table 3 of the ADF4355-3 datasheet (Absolute Maximum Ratings). You can power down VP and…
Dear SteveBeccue and ADI technical experts, Sorry to trouble you. After we read the AD9578 datasheet, we got confuse with below description, if the analysis progress is wrong please kindly help to correct it. a. In Page 26. calculation formula shows in Fractional Mode, b. In Page 28, we got register Settings for Various…(Show moreShow less)
Hi, My customer used AD9549 in holdover mode. She wants to reduce the re-locking time of AD9549 when REF_IN was supplied again after that did not been for a while. 1. Could you recommend a method to reduce the re-locking time in AD9549 except for changing internal loop filter bandwidth or Icp ? 2. Please recommend a new device that can set…(Show moreShow less)
Hi Paul kern, Thanks for your reply. The Time Threshold Programming Range of AD9548 is shorter than it of AD9549 as the below. In this case, my customer guess that the lock time of AD9348 is shorter than AD9549 or it would be able to set shorter. Is it right? Thanks in advance.
Hello, I designed a board from HMC7044 Eval Board schematic but I didn't manage to configure it correctly. I used both HMC7044 GUI and ADIsimCLK to get right register values but nothing happen. I tried to configure it like this : - OSC frequency 100 MHz (from an instrumentation square wave generator) - Output around 10 MHz on SCLK11 (output…(Show moreShow less)
Hi Loic, I have attached the modified version of your configuration file. -For input buffers "LVPECL" should be disabled if you are not using an LVPECL driver, that may distort the common-mode voltage. -In PLL1 section, signals going into "REF MUX & LOS" should be same. If the Prescaler is 1, the VCXO box should be 10. -Changed R1 as 2 and N1…
i am designing a frequency hopping sythesizer using HMC833. in the evaluation board schematic the "CP (pin 4)" output is given ti "VTUNE(pin 23)" via a loop filter. in the data sheet bw given is 74, 90, and 200 KHz. Can i use a different band width? how will i find the values of all the four capacitors and resistances? is there any simulation…(Show moreShow less)
The fundamental frequency range of the VCO on the HMC833 is 1.5 to 3GHz. This is the frequency range that the PLL will see. When outputting frequencies below 1.5GHz dividers are engaged at the output of the VCO, so the internal VCO frequency (which is fed back to the PLL) is still 1.5 to 3GHz. So a good compromise to cover the full 1.5 to 3GHz…
We are generating a 2000 MHz VCO frequency and then dividing by 4 to get 500 MHz. The output is phase locked. However, each time we power up, the 500 MHz signal can take one of four offsets relative to the REFIN because of the divide by 4. Is there anyway to lock the 500 MHz divided output to the REFIN rather than just the 2000 MHz VCO. From the…(Show moreShow less)
is there any fanout driver suited for the case (clock distribution) below? input: one pulse every second with 2.5v LVTTL (with a high level larger than 2V, a low level below 0.2V, a rising/fall time of 500 ps, a duration of 10 ns); at least 2 outputs: 2.5v LVTTL. Thank you for your kind help!
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