ad9361 FDD模式双口CMOS全双工1T1R。 读ENSM始终在alert状态，TXCP不能校准，不能进入FDD，也不能收发数据。

您好，咱们论坛中有许多关于AD9361的提问帖及解答，供您先参考下https://ezchina.analog.com/search.jspa?q=ad9361

谢谢！那些资料我之前都看过了。

我用的FPGA纯逻辑对ad9361进行参数配置，参考时钟是40M无源晶振。我需要设置RF LO 100MHz,ADC和DAC与BBP的接口速率都是30.72MHz,DDR速率，FDD,1T1R,CMOS,DDR,full duplex,enable pulse mode。

我目前遇到的问题是:

1. RF VCO tx:0x284[7],1 when done.But it can't be done when read the register value.However,the rx:0x247[7] is done.It means TXCP can't be correctly calibrated,but the RXCP calibration is done.
2. How to move alert to FDD?I’m using FDD,1T1R,CMOS,DDR,full duplex,enable pulse mode,Refclk is 40MHz.

I configured the register 0x012==0x02.After all register is configured,and I read the register’ s value 0x17==0x05,which means the ENSM is always in Alert state.I try to reconfigure the alert to FDD,but it is still keep in alert state.

can you offer a detail register map that can fit for my application? I use register map as follows:

//************************************************************
// AD9361 R2 Auto Generated Initialization Script:  This script was
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: LTE 20 MHz
// REFCLK_IN: 40.000 MHz

RESET_FPGA
RESET_DUT

BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
ReadPartNumber
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,2,2 // Sets local variables in script engine, user can ignore
SPIWrite 292,08 // Set DCXO Coarse Tune[5:0].  Coarse and Fine nominal values used with eval system.  Other nominal values may be needed in a customer system
SPIWrite 293,80 // Set DCXO Fine Tune [12:5]
SPIWrite 294,00 // Set DCXO Fine Tune [4:0]
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,07 // Enable Clocks
WAIT 20 // waits 20 ms

//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
SPIWrite 045,03 // Set BBPLL reflclk scale to REFCLK * 2
SPIWrite 046,02 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,14 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,2E // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,09 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,0C // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 172.800 us (Done when 0x05E[7]==1)

SPIRead 05E // Check BBPLL locked status  (0x05E[7]==1 is locked)

SPIWrite 002,4E // Setup Tx Digital Filters/ Channels
SPIWrite 003,5E // Setup Rx Digital Filters/ Channels
SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
SPIWrite 00A,09 // Set BBPLL post divide rate

//************************************************************
// AD9361 R2 Auto Generated Initialization Script:  This script was
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: LTE 20 MHz
// REFCLK_IN: 40.000 MHz

RESET_FPGA
RESET_DUT

BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
ReadPartNumber
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,2,2 // Sets local variables in script engine, user can ignore
SPIWrite 292,08 // Set DCXO Coarse Tune[5:0].  Coarse and Fine nominal values used with eval system.  Other nominal values may be needed in a customer system
SPIWrite 293,80 // Set DCXO Fine Tune [12:5]
SPIWrite 294,00 // Set DCXO Fine Tune [4:0]
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,07 // Enable Clocks
WAIT 20 // waits 20 ms

//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
SPIWrite 045,03 // Set BBPLL reflclk scale to REFCLK * 2
SPIWrite 046,02 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,14 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,2E // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,09 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,0C // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 172.800 us (Done when 0x05E[7]==1)

SPIRead 05E // Check BBPLL locked status  (0x05E[7]==1 is locked)

SPIWrite 002,4E // Setup Tx Digital Filters/ Channels
SPIWrite 003,5E // Setup Rx Digital Filters/ Channels
SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
SPIWrite 00A,09 // Set BBPLL post divide rate

//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
SPIWrite 010,C8 // I/O Config.  Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
SPIWrite 011,00 // I/O Config.  Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
SPIWrite 012,02 // I/O Config.  Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
SPIWrite 006,00 // PPORT Rx Delay (adjusts Tco Dataclk->Data)
SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data)

//************************************************************
// Setup RF PLL non-frequency-dependent registers
//************************************************************
SPIWrite 261,00 // Set Rx LO Power mode
SPIWrite 2A1,00 // Set Tx LO Power mode
SPIWrite 248,0B // Enable Rx VCO LDO
SPIWrite 288,0B // Enable Tx VCO LDO
SPIWrite 246,02 // Set VCO Power down TCF bits
SPIWrite 286,02 // Set VCO Power down TCF bits
SPIWrite 249,8E // Set VCO cal length
SPIWrite 289,8E // Set VCO cal length
SPIWrite 23B,80 // Enable Rx VCO cal
SPIWrite 27B,80 // Enable Tx VCO cal
SPIWrite 243,0D // Set Rx prescaler bias
SPIWrite 283,0D // Set Tx prescaler bias
SPIWrite 23D,00 // Clear Half VCO cal clock setting
SPIWrite 27D,00 // Clear Half VCO cal clock setting

SPIWrite 015,0C // Set Dual Synth mode bit
SPIWrite 014,15 // Set Force ALERT State bit
SPIWrite 013,01 // Set ENSM FDD mode
WAIT 1 // waits 1 ms

SPIWrite 23D,04 // Start RX CP cal
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1)

SPIWrite 27D,04 // Start TX CP cal
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1)

SPIWrite 23D,00 // Disable RX CP Calibration since the CP Cal start bit is not self-clearing.  Only important if the script is run again without restting the DUT
SPIWrite 27D,00 // Disable TX CP Calibration since the CP Cal start bit is not self-clearing.  Only important if the script is run again without restting the DUT
//************************************************************
// FDD RX,TX Synth Frequency: 100.000000,100.000000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 23A,4A // Set VCO Output level[3:0]
SPIWrite 239,C3 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 242,1F // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 238,78 // Set VCO Cal Offset[3:0]
SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 251,0C // Set VCO Varactor Reference[3:0]
SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
SPIWrite 23B,92 // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 23E,D4 // Set Synth Loop Filter C2 and C1
SPIWrite 23F,DF // Set Synth Loop Filter  R1 and C3
SPIWrite 240,09 // Set Synth Loop Filter R3

//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 27A,4A // Set VCO Output level[3:0]
SPIWrite 279,C3 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 282,1F // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 278,78 // Set VCO Cal Offset[3:0]
SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 291,0C // Set VCO Varactor Reference[3:0]
SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
SPIWrite 27B,92 // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 27E,D4 // Set Synth Loop Filter C2 and C1
SPIWrite 27F,DF // Set Synth Loop Filter  R1 and C3
SPIWrite 280,09 // Set Synth Loop Filter R3

//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0]
SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8]
SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16]
SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8]
SPIWrite 231,50 // Write Rx Synth Integer Freq Word[7:0]
SPIWrite 005,55 // Set LO divider setting
SPIWrite 273,00 // Write Tx Synth Fractional Freq Word[7:0]
SPIWrite 274,00 // Write Tx Synth Fractional Freq Word[15:8]
SPIWrite 275,00 // Write Tx Synth Fractional Freq Word[22:16]
SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8]
SPIWrite 271,50 // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
SPIWrite 005,55 // Set LO divider setting
SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked)
SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked)

您好，我想问下，TXCP和RXCP校准不应该是在ALERT状态下完成嘛？那为什么SPIWrite 014,15 // Set Force ALERT State bit
SPIWrite 013,01 // Set ENSM FDD mode，要把 ENSM设为FDD模式