HMC7044 输出时钟有个几十KHz的杂散

Question

HMC7044 输出时钟有个几十KHz的杂散，参考时钟100MHz， 输出时钟125MHz，查询寄存器PLL1 /PLL2都是锁定的。 
 该怎么消除这个几十KHz的杂散?

emrecangidik · Answer

Hi, 
 If you publish the question in English, maybe I can help with the spurs. 
 From my limited understanding of the translation, you are observing some spur issues at the output. You are using both PLL1 and PLL2. am I correct? 
 I don't recommend a filter to the output as it will degrade the performance of the output clock. You can decrease the charge pump current of PLL1 and PLL2 to reduce the spur. It may require some fine-tuning with charge pump values. You can try to change the PFD frequency of PLL1 and PLL2 to see if the spur is shifting out of the band. 
 Thanks, 
 Emrecan

Echen5 · Answer

Hi Jasper, 
 You can try Emrecan's suggestion for debugging, or tell me the configuration parameters of HMC7044, and I can try to reproduce your problem on EVB. 
 Thanks, 
 Elvin

Echen5 · Answer

Hi Jasper, 
 You can try Emrecan's suggestion for debugging, or tell me the configuration parameters of HMC7044, and I can try to reproduce your problem on EVB. 
 Thanks, 
 Elvin