HMC7044 输出时钟有个几十KHz的杂散,参考时钟100MHz, 输出时钟125MHz,查询寄存器PLL1 /PLL2都是锁定的。
该怎么消除这个几十KHz的杂散?
HMC7044 输出时钟有个几十KHz的杂散,参考时钟100MHz, 输出时钟125MHz,查询寄存器PLL1 /PLL2都是锁定的。
该怎么消除这个几十KHz的杂散?
可以在输出端添加滤波器抑制杂散,同时尽量使用相噪性能好的参考源。
Hi,
If you publish the question in English, maybe I can help with the spurs.
From my limited understanding of the translation, you are observing some spur issues at the output. You are using both PLL1…
Hi Jasper,
You can try Emrecan's suggestion for debugging, or tell me the configuration parameters of HMC7044, and I can try to reproduce your problem on EVB.
Thanks,
Elvin
Hi,
If you publish the question in English, maybe I can help with the spurs.
From my limited understanding of the translation, you are observing some spur issues at the output. You are using both PLL1 and PLL2. am I correct?
I don't recommend a filter to the output as it will degrade the performance of the output clock. You can decrease the charge pump current of PLL1 and PLL2 to reduce the spur. It may require some fine-tuning with charge pump values. You can try to change the PFD frequency of PLL1 and PLL2 to see if the spur is shifting out of the band.
Thanks,
Emrecan
Hi,
If you publish the question in English, maybe I can help with the spurs.
From my limited understanding of the translation, you are observing some spur issues at the output. You are using both PLL1 and PLL2. am I correct?
I don't recommend a filter to the output as it will degrade the performance of the output clock. You can decrease the charge pump current of PLL1 and PLL2 to reduce the spur. It may require some fine-tuning with charge pump values. You can try to change the PFD frequency of PLL1 and PLL2 to see if the spur is shifting out of the band.
Thanks,
Emrecan
Hi Emrecan,
Your understanding is correct. The customer found some spurs at the output and is looking for suggestions to improve the spur performance. Thank you for your suggestions.
Thanks
Elvin
emrecangidik , thanks very much.
I use HMC7044 with PLL1 and PLL2 enable.
I have tried to change the charge pump current of pll1 and pll2, but have no improvement.
PLL1 charge pump current now set 0x5, PLL2 set 0xF
I have change the PLL1 PFD frequency from 10M, 5M ,2.5M ,1.25M .... it have no improvement.
PLL2 PFD frequency now is 100M , when i change the PFD freq to 200M , PLL2 is unlocked.
when i change the PFD freq to 10M , the spurs become very big.
After HMC7044 finish config, the HMC7044 ref clock in can observe 26K spurs, but when i set HMC7044 to sleep mode. the spurs
in ref clock disappears.
I suspect the PCB ground of HMC7044 have some problems, but have not find the proof.
Hi Jasper,
If the charge pump and PFD frequency are changed and the spur size does not change, it indicates that the spur is not originating from within the PLL loops. I suggest investigating the VCO supply and Output buffer supplies for any potential issues. How is the supply for HMC7044 being provided? Is a switch-mode power supply or an LDO being used?
Thanks,
Emrecan
I use LTM4644 and LT1963 to provide the 3.3V supply of HMC7044; now I find LTM4644 output have some nosie of 26KHz;i bypass LTM4644,the spurs disappear