ADF4159 MUXOUT输出

Question

有一个ADF4159 MUXOUT输出的问题想问一下大家。 
 我用的是50M的参考时钟，分频器型号为ADF4159CCPZ-RL7，VCO型号为HMC1167，寄存器从R7到R0分别设置的是 
 0x7 0x6 0x5 0x4 0x384C3 0x7108002 0x1 0x181CC000 
 想在MUXOUT引脚R-DIVIDER模式输出25Mhz的频率，但是不论怎么修改R0寄存器，R-DIVIDER模式出来的都是1.56Mhz，咨询一下各位如何解决 
 求教，感谢

emrecangidik · Accepted Answer

Hi, 
 
 I have a couple of questions about your setup. When I checked your register settings, I saw you are using R-Doubler on (REG2[20]=1). This means that your PFD frequency is 100 MHz. is PLL getting locked? 
 What is your VCO frequency? With your register settings, I calculated that it is 11500MHZ and you are using Fvco/2 as input of PLL. 11500 MHZ is outside of operation limits of HMC1167 Are you using the evaluation board or custom PCB? If you are using an Evaluation board, I recommend using ADF4158/59 PLL Evaluation Software GUI to check if register values are correct. R Divider output shouldn't depend on lock status or other N divider settings, but I want to ensure that SPI communication is established. Can you select different mux output types and check whether you can control mux output? For example, you can set mux output as a DVdd or GND and measure the output voltage. You can set mux output as Digital Lock Detect to see if PLL is locked. 
 Regards, Emrecan)