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AD9528 PLL2 配置


  • Hi Bit2021,

    Please provide your configuration file to us. We can help to check it and might run it in the lab for verification if needed. You can mail me directly on I based at China as Clock AE. 

    Two more comments here: 1) The 10M is not optimized and recommend freq as the PLL2 PFD rate but it should work. You can enable the doubler to get the PFD work at 20M to improve the phase noise if your OCXO have good duty cycle. 2)Have you ever check the PLL2 lock status while your testing the 1.1x output freq? Please confirm.