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AD9528 PLL2 配置

您好!我想跳过AD9528的第一级锁相环,通过外接一个10M的OCXO直接输入到第二级锁相环,最终输出125MHz和3.90625MHz的时钟频率,但是我们设置好分频系数之后,用频谱仪测得实际频率为137.65MHz和4.3MHz,正好是我们需要频率的额1.1倍,我们不清楚问题出现在哪里,希望得到您的帮助!

  • Hi Bit2021,

    Please provide your configuration file to us. We can help to check it and might run it in the lab for verification if needed. You can mail me directly on jim.sang@analog.com. I based at China as Clock AE. 

    Two more comments here: 1) The 10M is not optimized and recommend freq as the PLL2 PFD rate but it should work. You can enable the doubler to get the PFD work at 20M to improve the phase noise if your OCXO have good duty cycle. 2)Have you ever check the PLL2 lock status while your testing the 1.1x output freq? Please confirm.