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a question about how should i determine the value of a loop filter uesd in a cppll?can i use the software "ADIsimCLK"?

in the next project, i want to use the chip"AD9528", a clock generator.clock refA is 30.72MHz,external VCXO is 122.88MHz(crystek cvhd-950),and i want a output with 122.88MHz, a output with 30.72MHz,but i dont know if i used the software  "ADIsimCLK" in the right way.

could somebody tell me a way to determine loop bandwidth and phase margin?

i think the phase margin is usually set to 50° at the begining of a design,does it right?

and how about loop bandwidth?