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a question about how should i determine the value of a loop filter uesd in a cppll?can i use the software "ADIsimCLK"?

in the next project, i want to use the chip"AD9528", a clock generator.clock refA is 30.72MHz,external VCXO is 122.88MHz(crystek cvhd-950),and i want a output with 122.88MHz, a output with 30.72MHz,but i dont know if i used the software  "ADIsimCLK" in the right way.

could somebody tell me a way to determine loop bandwidth and phase margin?

i think the phase margin is usually set to 50° at the begining of a design,does it right?

and how about loop bandwidth?

  • Looking at what you have done, you have successfully configured the software for your frequencies, but you have the loop bandwidth of PLL1 set to 30MHz.  PLL1 is normally very narrow band, maybe 30Hz bandwidth.

    I'd suggest that you start with a new design, choose the AD9528, then on the config screen change R1 to 8 (to change the ref to 30.72MHz), on the VCXO selection screen choose 'search libraries' and then choose the CVHD-950, and simply accept the defaults on the rest of the screens.  This will give you a basic design that you could optimize whilst monitoring the phase noise and jitter.  You can set the output dividers in the  data panel, for example increase the OUT0 divider to 8 to get your 122.88MHz output.

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