HMC987 clock buffer, output power only -15dBm

This buffer is used for local oscillator synchronization of multi-chip AD9361, using a single-ended output. The AD9361 can work normally when the actual test is under 5G, but the AD9361 will work abnormally when the test is over 5G. The whole band output Only-15dbm, can not meet the local oscillator requirements of-3 to 3DBM power, is the schematic design error or the register is not properly configured?