I have a question about the following passage in the Clocks & Timing ICs Evaluation Kit User Manual.

"The HMC1033/HMC1035 evaluation board includes a precision PLL which generates a 50 MHz

clock locked to an externally supplied 10 MHz reference. The PLL design is an HMC1031 phase/
frequency detector, passive loop filter and a low noise 50 MHz VCXO. The PLL is normally, or
default upon shipping, set to lock on to a 10 MHz reference feed into “REF IN”. A 5 MHz input
reference can be used if D1, D0 is reconfigured to “1,1”, or 50 MHz if D1, D0 is reconfigured to
“0,1”. The “REF IN” would normally have a +/-50 ppm tolerance which falls within the VCXO pull
range. Although not recommended, the HMC1033/HMC1035 Eval Board can be operated without
supplying an external reference, and the PLL will pull the VCXO to about 49.992 MHz, or 180
ppm low. Alternatively, an external reference can be feed into the HMC1033/HMC1035 evaluation
board which requires removing C44,C35, R32 and J6, the TPLL/TCXO Jumper, and placing a 0
Ohm resistor in the R20 and R36 locations. See Evaluation PCB Schematic for more details. The
HMC1032/HMC1034 eval boards have a 50 MHz crystal oscillator and do not require an external


If I want to externally input a standard reference signal of 10MHz from a cesium clock

should I directly input the reference signal? Or Still need to removing C44,C35, R32 and 

J6, the TPLL/TCXO Jumper, and placing a 0 Ohm resistor in the R20 and R36 locations?