Tech experts, I am currently developing a frequency source. The HMC7044 outputs different reference clocks to the ADF5355 to minimize integer boundary spurs. Eventually, a 6.8 - 13.6 GHz frequency is generated at the single-ended output port RFoutB of the ADF5355.
I would like to ask the following three questions:
1. Register writing issue
2. Setting of the external loop filter (for rapid locking)
3. Settings related to MUXOUT
<1>.Register writing issue
Currently, the clock output from the HMC7044 is normal in LVDS format, with a range of 2400 MHz/N, where N is an even integer from 20 to 30. The 32 is not used to avoid the register write mode in the datasheet where fPFD ≤ 75 MHz. All use the register write mode where fPFD > 75 MHz, that is

Considering that my REFIN is changing, and thus fPFD will also change, since the Reg9 and Reg6 sections will change according to fPFD, can the write operation for frequency changes be directly incorporated into the register changes of Reg10 and Reg4, including the changes of Reg9 and Reg6? That is
<2>Setting of the external loop filter (for rapid locking)
In addition, to verify whether the ADF5355 has successfully locked phase, I tested the voltage at the Vtune pin. I tried it with different output signals and different fPFD values. I found that only when fPFD = 80 MHz, the voltage at the Vtune pin was a stable 2.46 V, while in other cases it was around 0.34 V or 4.64 V. Does this mean that the former has successfully locked phase and the latter has not?
Also, for my loop filter circuit, I set ADIsimPLL as shown in the figure (hardware circuit requires CPP_3C):

<3>Settings related to MUXOUT
For the MUXOUT setting of DB29-DB27 in register 4, if I want to check whether the phase-locked loop is locked, I can directly set it to 1 1 0 (digital lock detect), and after setting DB8 (LDP) to 3.3V, I can directly measure the MUXOUT pin of ADF5355 with a scope or multimeter to determine whether it is 3.3V to confirm the lock status?

Edit Notes
Seeking advice from technical experts regarding the register configuration and phase-locking verification of ADF5355[edited by: Rxstar at 1:47 PM (GMT -5) on 13 Dec 2025]