max96724 Video line CRC error detected

yxyy3604
on Aug 25, 2025
Category: Hardware
Product Number: MAX96724
在使用max96717f和max96724的项目中，采用Tunnelling模式，max96724的0x100寄存器的值为0xb2，查询手册得知含义为”Video line CRC error detected“，请问这个问题要怎么解决？
这是我是用的配置脚本
#//  
#// CSIConfigurationTool
#//  
#// GMSL-A / Serializer: MAX96717F (Tunnel Mode) / Mode: 1x4 / Device Address: 0x80 / Multiple-VC Case: Single VC / Pipe Sharing: Separate Pipes
#// PipeZ:
#// Input Stream: VC0 RAW12 PortB (D-PHY)

#// Deserializer: MAX96724 / Mode: 1x4A + 2x2 / Device Address: 0x4E
#// Pipe0:
#// GMSL-A Input Stream: VC0 RAW12 PortB - Output Stream: VC0 RAW12 PortA (D-PHY)

i2ctransfer -f -y 2 w3@0x27 0x04 0x0B 0x00   #// BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output disabled
#// Link Initialization for Deserializer
i2ctransfer -f -y 2 w3@0x27 0x00 0x06 0xF1   #// DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | LINK_EN_B (LINK_EN_B): Disabled | LINK_EN_C (LINK_EN_C): Disabled | LINK_EN_D (LINK_EN_D): Disabled
i2ctransfer -f -y 2 w3@0x27 0x00 0x10 0x21   #// DEV : REG26 | RX_RATE_PHYA (RX_RATE_PHYA): 3
i2ctransfer -f -y 2 w3@0x27 0x00 0x18 0x01   #// TOP_CTRL : CTRL1 | RESET_ONESHOT_A (RESET_ONESHOT_A): Activated
sleep 0.12 # #// 120 msec delay
#// Link Initialization for Deserializer
i2ctransfer -f -y 2 w3@0x27 0x00 0x06 0xF1   #// DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | (Default) LINK_EN_B (LINK_EN_B): Disabled | (Default) LINK_EN_C (LINK_EN_C): Disabled | (Default) LINK_EN_D (LINK_EN_D): Disabled
i2ctransfer -f -y 2 w3@0x27 0x00 0x03 0xFE   #// DEV : REG3 | (Default) DIS_REM_CC_A (GMSL Link A I2C Port 0): Enabled | DIS_REM_CC_B (GMSL Link B I2C Port 0): Disabled | DIS_REM_CC_C (GMSL Link C I2C Port 0): Disabled | DIS_REM_CC_D (GMSL Link D I2C Port 0): Disabled
sleep 0.12 # #// 120 msec delay
#// Video Transmit Configuration for Serializer(s)
i2ctransfer -f -y 2 w3@0x40 0x00 0x02 0x03   #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
#//  
#// INSTRUCTIONS FOR GMSL-A SERIALIZER MAX96717F
#//  
#// MIPI D-PHY Configuration
i2ctransfer -f -y 2 w3@0x40 0x03 0x30 0x40   #// MIPI_RX : MIPI_RX0 | (Default) RSVD (Port Configuration): 1x4
i2ctransfer -f -y 2 w3@0x40 0x03 0x83 0x80   #// MIPI_RX_EXT : EXT11 | (Default) Tun_Mode (Tunnel Mode): Enabled
i2ctransfer -f -y 2 w3@0x40 0x03 0x31 0x30   #// MIPI_RX : MIPI_RX1 | (Default) ctrl1_num_lanes (Port B - Lane Count): 4
i2ctransfer -f -y 2 w3@0x40 0x03 0x32 0xE0   #// MIPI_RX : MIPI_RX2 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
i2ctransfer -f -y 2 w3@0x40 0x03 0x33 0x04   #// MIPI_RX : MIPI_RX3 | (Default) phy2_lane_map (Lane Map - PHY2 D0): Lane 0 | (Default) phy2_lane_map (Lane Map - PHY2 D1): Lane 1
i2ctransfer -f -y 2 w3@0x40 0x03 0x34 0x00   #// MIPI_RX : MIPI_RX4 | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal
i2ctransfer -f -y 2 w3@0x40 0x03 0x35 0x00   #// MIPI_RX : MIPI_RX5 | (Default) phy2_pol_map (Polarity - PHY2 Lane 0): Normal | (Default) phy2_pol_map (Polarity - PHY2 Lane 1): Normal | (Default) phy2_pol_map (Polarity - PHY2 Clock Lane): Normal
#// Controller to Pipe Mapping Configuration
i2ctransfer -f -y 2 w3@0x40 0x03 0x08 0x64   #// FRONTTOP : FRONTTOP_0 | (Default) RSVD (CLK_SELZ): Port B | (Default) START_PORTB (START_PORTB): Enabled
i2ctransfer -f -y 2 w3@0x40 0x03 0x11 0x40   #// FRONTTOP : FRONTTOP_9 | (Default) START_PORTBZ (START_PORTBZ): Start Video
#// Pipe Configuration
i2ctransfer -f -y 2 w3@0x40 0x00 0x5B 0x00   #// CFGV__VIDEO_Z : TX3 | TX_STR_SEL (TX_STR_SEL Pipe Z): 0x0
#//  
#// INSTRUCTIONS FOR DESERIALIZER MAX96724
#//  
#// Video Pipes And Routing Configuration
i2ctransfer -f -y 2 w3@0x27 0x00 0xF0 0x60   #// VIDEO_PIPE_SEL : VIDEO_PIPE_SEL_0 | (Default) VIDEO_PIPE_SEL_0 (Pipe 0 GMSL2 PHY): A | VIDEO_PIPE_SEL_0 (Pipe 0 Input Pipe): X
i2ctransfer -f -y 2 w3@0x27 0x00 0xF4 0x01   #// VIDEO_PIPE_SEL : VIDEO_PIPE_EN | (Default) VIDEO_PIPE_EN (Video Pipe 0): Enabled | VIDEO_PIPE_EN (Video Pipe 1): Disabled | VIDEO_PIPE_EN (Video Pipe 2): Disabled | VIDEO_PIPE_EN (Video Pipe 3): Disabled | STREAM_SEL_ALL (Stream Select All): Disabled
#// MIPI D-PHY Configuration
i2ctransfer -f -y 2 w3@0x27 0x08 0xA0 0x08   #// MIPI_PHY : MIPI_PHY0 | phy_4x2 (Port Configuration): 1x4A + 2x2
i2ctransfer -f -y 2 w3@0x27 0x09 0x4A 0xD0   #// MIPI_TX__1 : MIPI_TX10 | (Default) CSI2_LANE_CNT (Port A - Lane Count): 4
i2ctransfer -f -y 2 w3@0x27 0x08 0xA3 0xE4   #// MIPI_PHY : MIPI_PHY3 | (Default) phy0_lane_map (Lane Map - PHY0 D0): Lane 0 | (Default) phy0_lane_map (Lane Map - PHY0 D1): Lane 1 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
i2ctransfer -f -y 2 w3@0x27 0x08 0xA5 0x00   #// MIPI_PHY : MIPI_PHY5 | (Default) phy0_pol_map (Polarity - PHY0 Lane 0): Normal | (Default) phy0_pol_map (Polarity - PHY0 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Clock Lane): Normal
i2ctransfer -f -y 2 w3@0x27 0x09 0x43 0x07   #// MIPI_TX__1 : MIPI_TX3 | DESKEW_INIT (Controller 1 Auto Initial Deskew): Disabled
i2ctransfer -f -y 2 w3@0x27 0x09 0x44 0x01   #// MIPI_TX__1 : MIPI_TX4 | DESKEW_PER (Controller 1 Periodic Deskew): Disabled
i2ctransfer -f -y 2 w3@0x27 0x1D 0x00 0xF4   #//  (config_soft_rst_n - PHY1): 0x0
#// This is to set predefined (coarse) CSI output frequency
#// CSI Phy 1 is 1500 Mbps/lane.
i2ctransfer -f -y 2 w3@0x27 0x1D 0x00 0xF4   #// (Default) 
i2ctransfer -f -y 2 w3@0x27 0x04 0x18 0x2F   #// (Default) 
i2ctransfer -f -y 2 w3@0x27 0x1D 0x00 0xF5   #//  | (Default)  (config_soft_rst_n - PHY1): 0x1
i2ctransfer -f -y 2 w3@0x27 0x08 0xA2 0x34   #// MIPI_PHY : MIPI_PHY2 | phy_Stdby_n (phy_Stdby_2): Put PHY2 in standby mode | phy_Stdby_n (phy_Stdby_3): Put PHY3 in standby mode
#// Tunnel Mode Configuration
i2ctransfer -f -y 2 w3@0x27 0x08 0xCA 0xE5   #// MIPI_PHY : MIPI_CTRL_SEL | MIPI_CTRL_SEL_0 (MIPI Controller Pipe 0): 0x1
i2ctransfer -f -y 2 w3@0x27 0x09 0x39 0x10   #// MIPI_TX__0 : MIPI_TX57 | (Default) TUN_DEST (Tunneling Destination Pipe 0): 0x1
i2ctransfer -f -y 2 w3@0x27 0x09 0x36 0x09   #// MIPI_TX__0 : MIPI_TX54 | TUN_EN (Pipe 0 Tunnel Mode): Enabled
i2ctransfer -f -y 2 w3@0x27 0x09 0x39 0x50   #// MIPI_TX__0 : MIPI_TX57 | DIS_AUTO_TUN_DET (Pipe 0 Disable Auto Tunnel Detection): Enabled
i2ctransfer -f -y 2 w3@0x27 0x08 0xCA 0xE5   #// MIPI_PHY : MIPI_CTRL_SEL | (Default) MIPI_CTRL_SEL_1 (MIPI Controller Pipe 1): 0x1
i2ctransfer -f -y 2 w3@0x27 0x09 0x79 0x10   #// MIPI_TX__1 : MIPI_TX57 | (Default) TUN_DEST (Tunneling Destination Pipe 1): 0x1
i2ctransfer -f -y 2 w3@0x27 0x04 0x0B 0x02   #// BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output enabled
#// Video Transmit Configuration for Serializer(s)
i2ctransfer -f -y 2 w3@0x40 0x00 0x02 0x43   #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled