Category: Software
Product Number: AD9176
Hello! I'm seeking help! Thank you!
We have made a board by ourselves. There are two AD9176 chips and one FPGA on the board. Their dclk (300M) and sysref (3.75M) come from the same clock chip 04828 (the clock outputs have been synchronized).
The relevant configuration information of AD9176 is as follows:
- Use mode 10, with the output from DAC0. The sysref is a 3.75M continuous signal. The DAC sampling clock is 9.6G. The reference clock of the internal pll is 300M. The channel datapaths are bypassed. The main DAC datapaths use 4x interpolation, and the NCO of the main DAC datapaths is 3.6G.
- Except for 0x113 = 04, the configurations of all other registers are carried out in the order of the START-UP SEQUENCE provided in the manual.
- Currently, both AD9176 chips can successfully output signals in the range of 2.6 - 4.6G.
Problems encountered:
- I have performed an "AND" operation on the YNC signals of the two AD9176 chips in the FPGA. However, every time the power is turned on, the output phases of the two AD9176 chips are not synchronized.
I would like to ask, when synchronizing multiple chips, are there any additional register configurations required? Or what is the recommended way to perform multi-chip synchronization?
The following is my code configuration process:
//1 Power-Up and Required Register Writes
rom_data[000] <= { 1'b0, 15'h000, 8'h81} ;
rom_data[001] <= { 1'b0, 15'h000, 8'h00} ; //解复位，set 3 wire spi
//WAIT 200ms
rom_data[002] <= { 1'b0, 15'h091, 8'h00} ;
rom_data[003] <= { 1'b0, 15'h206, 8'h01} ;
rom_data[004] <= { 1'b0, 15'h705, 8'h01} ;
rom_data[005] <= { 1'b0, 15'h090, 8'h02} ;
//8'h00 ////8'h02 DAC1 PD DAC0 PO
//2. DAC pll 配置
//Required Device Configurations
rom_data[006] <= { 1'b0, 15'h095, 8'h00} ; //1: Bypass PLL ,0:use PLL
rom_data[007] <= { 1'b0, 15'h790, 8'h00} ;
rom_data[008] <= { 1'b0, 15'h791, 8'h00} ;
rom_data[009] <= { 1'b0, 15'h796, 8'hE5} ;
rom_data[010] <= { 1'b0, 15'h7A0, 8'hBC} ;
rom_data[011] <= { 1'b0, 15'h794, 8'h08} ; // 设置 DAC PLL 电荷泵电流。建议设置为 0x08，但对于不同的相位噪声性能目标，范围可以是 0x04 至 0x10。
rom_data[012] <= { 1'b0, 15'h797, 8'h10} ;
rom_data[013] <= { 1'b0, 15'h797, 8'h20} ;
rom_data[014] <= { 1'b0, 15'h798, 8'h10} ;
rom_data[015] <= { 1'b0, 15'h7A2, 8'h7F} ;
//WAIT 200ms
//Configure the DAC PLL,此处部分寄存器根据实际需求并结合手册进行设置
rom_data[016] <= { 1'b0, 15'h799, 8'h04} ;
rom_data[017] <= { 1'b0, 15'h793, 8'h18} ;
rom_data[018] <= { 1'b0, 15'h094, 8'h00} ;
rom_data[019] <= { 1'b0, 15'h792, 8'h02} ; //Reset VCO.
rom_data[020] <= { 1'b0, 15'h792, 8'h00} ;
//WAIT 200ms
rom_data[021] <= { 1'b1, 15'h7B5, 8'h01} ;// 读 0x7B5[0] Ensure PLL is locked by reading back a value of 1 for bit 0 of this register.
//3. Delay Lock Loop （DLL）延迟锁定环 配置
rom_data[022] <= { 1'b0, 15'h0C0, 8'h00} ;
rom_data[023] <= { 1'b0, 15'h0DB, 8'h00} ;
rom_data[024] <= { 1'b0, 15'h0DB, 8'h01} ;
rom_data[025] <= { 1'b0, 15'h0DB, 8'h00} ;
rom_data[026] <= { 1'b0, 15'h0C1, 8'h68} ;
rom_data[027] <= { 1'b0, 15'h0C1, 8'h69} ;
rom_data[028] <= { 1'b0, 15'h0C7, 8'h00} ;
rom_data[029] <= { 1'b0, 15'h0C7, 8'h01} ;
//WAIT 200ms
rom_data[030] <= { 1'b1, 15'h0C3, 8'h01} ; //通过读回该寄存器的位 0 的值 1 来确保 DLL 已被锁定。
//SYSREF± jitter window
rom_data[031] <= { 1'b0, 15'h039, 8'h04} ;//SYSREF± Jitter Window Tolerance = ±4 DAC Clock Cycles
rom_data[032] <= { 1'b0, 15'h036, 8'h02} ;//SYSREF± count
//full-scale current IOUTFS = 15.625 mA + FSC_CTRL × (25/256) (mA) 15.625 mA to 25.977
rom_data[033] <= { 1'b0, 15'h05A, 8'h6A} ;
//4. Calibration
rom_data[034] <= { 1'b0, 15'h050, 8'h2A} ;
rom_data[035] <= { 1'b0, 15'h061, 8'h68} ;
rom_data[036] <= { 1'b0, 15'h051, 8'h82} ;
rom_data[037] <= { 1'b0, 15'h051, 8'h83} ;
rom_data[038] <= { 1'b0, 15'h081, 8'h03} ;
//5. JESD204B Mode setup
rom_data[039] <= { 1'b0, 15'h100, 8'h00} ;
rom_data[040] <= { 1'b0, 15'h110, 8'h0A} ; //JESD_MODE 10
rom_data[041] <= { 1'b0, 15'h111, 8'h41} ; //DP_INTERP_MODE 主路径插值x4 ///// CH_INTERP_MODE channel旁路
rom_data[042] <= { 1'b0, 15'h084, 8'h00} ; //SYSREF_INPUTMODE AC SYSREF_PD 0
rom_data[043] <= { 1'b0, 15'h312, 8'h04} ; //根据所选模式设置 SYNCOUTx± 错误持续时间。
rom_data[044] <= { 1'b0, 15'h300, 8'h00} ; //[1:0]Enables the links。
rom_data[045] <= { 1'b0, 15'h475, 8'h09} ; //软复位 JESD204B 四字节解帧器。
rom_data[046] <= { 1'b0, 15'h453, 8'h07} ; //[7]= disable scrambling L-1 =7
rom_data[047] <= { 1'b0, 15'h458, 8'h2F} ; //Subclass 1 //NP value
rom_data[048] <= { 1'b0, 15'h454, 8'h00} ; // jesd204b F-1
// 其他值M S K...默认值是匹配的
rom_data[049] <= { 1'b0, 15'h475, 8'h01} ; //使 JESD204B 四字节解帧器退出复位状态。
//6. Main DAC Datapath
rom_data[050] <= { 1'b0, 15'h008, 8'h40} ; //[7:6] DAC0 选择要同时编程的主 DAC 数据路径
rom_data[051] <= { 1'b0, 15'h112, 8'h08} ; //[3] enable NCO.[0] 通道 NCO 根据主数据路径 NCO 更新请求重置或更新其 FTW。
rom_data[052] <= { 1'b0, 15'h114, 8'h00} ;
rom_data[053] <= { 1'b0, 15'h115, 8'h00} ;
rom_data[054] <= { 1'b0, 15'h116, 8'h00} ;
rom_data[055] <= { 1'b0, 15'h117, 8'h00} ;
rom_data[056] <= { 1'b0, 15'h118, 8'h00} ;
rom_data[057] <= { 1'b0, 15'h119, 8'h60} ; //3.6G NCO //// DDSM_FTW = (fCARRIER/fDAC) × 2^48
rom_data[058] <= { 1'b0, 15'h11C, 8'h00} ;
rom_data[059] <= { 1'b0, 15'h11D, 8'h00} ;
rom_data[060] <= { 1'b0, 15'h113, 8'h00} ; //113 DDSM_FTW_ LOAD_REQ 是主路径的 Update all NCO phase and FTW words.
rom_data[061] <= { 1'b0, 15'h113, 8'h00} ; //05 0R 01 Update all NCO phase and FTW words.
rom_data[062] <= { 1'b0, 15'h113, 8'h04} ;
//7. JESD204B SERDES Required Interface Setup
rom_data[063] <= { 1'b0, 15'h240, 8'hAA} ;
rom_data[064] <= { 1'b0, 15'h241, 8'hAA} ;
rom_data[065] <= { 1'b0, 15'h242, 8'h55} ;
rom_data[066] <= { 1'b0, 15'h243, 8'h55} ;
rom_data[067] <= { 1'b0, 15'h244, 8'h1F} ;
rom_data[068] <= { 1'b0, 15'h245, 8'h1F} ;
rom_data[069] <= { 1'b0, 15'h246, 8'h1F} ;
rom_data[070] <= { 1'b0, 15'h247, 8'h1F} ;
rom_data[071] <= { 1'b0, 15'h248, 8'h1F} ;
rom_data[072] <= { 1'b0, 15'h249, 8'h1F} ;
rom_data[073] <= { 1'b0, 15'h24A, 8'h1F} ;
rom_data[074] <= { 1'b0, 15'h24B, 8'h1F} ;
//***************************************************//
rom_data[075] <= { 1'b0, 15'h201, 8'h00} ; // Power down unused PHYs
rom_data[076] <= { 1'b0, 15'h203, 8'h01} ; //single-link mode, set to 0x01
rom_data[077] <= { 1'b0, 15'h253, 8'h00} ;//253 // 1:(lvds) For CMOS output on SYNCOUT0+, set Bit 0 to 0.
rom_data[078] <= { 1'b0, 15'h254, 8'h00} ;//254 // 1 For CMOS output on SYNCOUT0+, set Bit 0 to 0.
rom_data[079] <= { 1'b0, 15'h210, 8'h16} ;//210 //16
rom_data[080] <= { 1'b0, 15'h216, 8'h05} ;//216 //05
rom_data[081] <= { 1'b0, 15'h212, 8'hFF} ;//212 //FF
rom_data[082] <= { 1'b0, 15'h212, 8'h00} ;//212 //00
rom_data[083] <= { 1'b0, 15'h210, 8'h87} ;//210 //87
rom_data[084] <= { 1'b0, 15'h216, 8'h11} ;//216 //11
rom_data[085] <= { 1'b0, 15'h213, 8'h01} ;//213 //01
rom_data[086] <= { 1'b0, 15'h213, 8'h00} ;//213 //00
rom_data[087] <= { 1'b0, 15'h200, 8'h00} ;//200 //00
//WAIT 200ms
rom_data[088] <= { 1'b0, 15'h210, 8'h86} ;
rom_data[089] <= { 1'b0, 15'h216, 8'h40} ;
rom_data[090] <= { 1'b0, 15'h213, 8'h01} ;
rom_data[091] <= { 1'b0, 15'h213, 8'h00} ;
rom_data[092] <= { 1'b0, 15'h210, 8'h86} ;
rom_data[093] <= { 1'b0, 15'h216, 8'h00} ;
rom_data[094] <= { 1'b0, 15'h213, 8'h01} ;
rom_data[095] <= { 1'b0, 15'h213, 8'h00} ;
rom_data[096] <= { 1'b0, 15'h210, 8'h87} ;
rom_data[097] <= { 1'b0, 15'h216, 8'h01} ;
rom_data[098] <= { 1'b0, 15'h213, 8'h01} ;
rom_data[099] <= { 1'b0, 15'h213, 8'h00} ;
rom_data[100] <= { 1'b0, 15'h280, 8'h05} ;
rom_data[101] <= { 1'b0, 15'h280, 8'h01} ; //Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration.
//WAIT 200MS // Ensure 281 Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked
rom_data[102] <= { 1'b1, 15'h281, 8'h01} ; //SERDSES PLL locked
//8.Transport Layer Setup, Synchronization, and Enable Links
rom_data[103] <= { 1'b0, 15'h308, 8'h08} ; //corssbar
rom_data[104] <= { 1'b0, 15'h309, 8'h1A} ;
rom_data[105] <= { 1'b0, 15'h30A, 8'h2C} ;
rom_data[106] <= { 1'b0, 15'h30B, 8'h3E} ;
rom_data[107] <= { 1'b0, 15'h306, 8'h0C} ; //LMFC_VAR_0
rom_data[108] <= { 1'b0, 15'h307, 8'h0C} ;
rom_data[109] <= { 1'b0, 15'h304, 8'h02} ;
rom_data[110] <= { 1'b0, 15'h305, 8'h02} ; //LMFC_DELAY_1
rom_data[111] <= { 1'b0, 15'h03B, 8'hF1} ; //启用同步逻辑，并设置旋转模式以在同步重置触发时重置同步逻辑。
rom_data[112] <= { 1'b0, 15'h03A, 8'h02} ; // [1] Set up sync for one-shot sync mode 可读[4] 看是否同步完成
//WAIT 200MS wait SYSREF±
rom_data[113] <= { 1'b0, 15'h300, 8'h01} ;//SIGNLE LINK MODE 01: LINK0_EN
// //8. OUTPUT txen
rom_data[114] <= { 1'b0, 15'h085, 8'h13} ;
rom_data[115] <= { 1'b0, 15'h1DE, 8'h03} ;
rom_data[116] <= { 1'b0, 15'h008, 8'hC0} ;
rom_data[117] <= { 1'b0, 15'h596, 8'h0C} ;
rom_data[118] <= { 1'b1, 15'h024, 8'h00} ;Thread Notes
__CommunityServer__Service__ - Moved from High-Speed DACs to Other Products (CN). Post date updated from Thursday, January 9, 2025 12:04 PM UTC to Thursday, January 9, 2025 12:04 PM UTC to reflect the move.
