LVDS隔离电路ADN4650输出异常

请提供原理图和测试波形。 

Schematic diagram

A narrow pulse of 20ns is split into two paths and sent to the positive input terminal of AD8465. The negative terminal is set with a threshold voltage DC bias of 1.2V. The SHDN terminal of AD8465 is connected to +5V, and the LE terminal is left floating. The output differential signal is sent to the two differential input terminals of ADN4650.

Test diagram:

A 20ns pulse with an amplitude of 1.2V is input to the positive terminal of AD8465, and the negative terminal is set with a voltage bias of 1.2V.

Figure 1 shows the positive input of AD8465 and the positive output of AD8465, with the oscilloscope in persistence mode. The positive input of AD8465 receives a 20ns pulse with an amplitude of 1.2V, while the negative terminal has a voltage bias of 1.2V. The output is a positive-negative-positive pulse.

Figure 2 shows the positive end input signal of the AD8465 and the differential output signal of the AD4650, with the oscilloscope set in afterglow mode. The output from the AD4650 is predominantly positive and negative pulse signals, with occasional abnormal signals of 800ns in width. The current issue is the cause of this 800ns pulse signal; any insights would be appreciated.

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这个器件应该是用于lvds的， lvds应该是电流驱动的， 

电流在终端电阻两端产生差分电压。 

您将其当作比较器应该是错误的