max96717f与max96712传输数据问题

Question

我们公司正在研发一款雷达产品，其中雷达输出的数据经过max96717f加串后再max96712解串，最后给到nvidia的Jetson orin nx 平台处理，但是max96712的mipi csi端口没有输出。 
 
 查看max96712的0x108寄存器=0x62 意思是&rdquo;Video pipeline locked&ldquo;，0 x1dc寄存器=0x81 意思是&rdquo;Video channel is locked &ldquo; 
 还有些其它寄存器的值，其中设备0x29为max96712，0x40为max96717f。 
 
 这是我正在使用的配置脚本 
 #// 
#// CSIConfigurationTool
#// 
#// GMSL-A / Serializer: MAX96717F (Pixel Mode) / Mode: 1x4 / Device Address: 0x80 / Multiple-VC Case: Single VC / Pipe Sharing: Separate Pipes
#// PipeZ:
#// Input Stream: VC0 RAW12 PortB (D-PHY) (Doubled)

#// GMSL-B / Serializer: MAX96717F (Pixel Mode) / Mode: 1x4 / Device Address: 0x84 / Multiple-VC Case: Single VC / Pipe Sharing: Separate Pipes
#// PipeZ:
#// Input Stream: VC0 RAW12 PortB (D-PHY) (Doubled)

#// Deserializer: MAX96712 / Mode: 1x4A + 2x2 / Device Address: 0x4E
#// Pipe0:
#// GMSL-A Input Stream: VC0 RAW12 PortB - Output Stream: VC0 RAW12 PortA (D-PHY)
#// Pipe1:
#// GMSL-B Input Stream: VC0 RAW12 PortB - Output Stream: VC1 RAW12 PortA (D-PHY)

i2ctransfer -f -y 2 w3@0x29 0x04 0x0B 0x00 #// BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output disabled
#// Link Initialization for Deserializer
i2ctransfer -f -y 2 w3@0x29 0x00 0x06 0xF3 #// DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | (Default) LINK_EN_B (LINK_EN_B): Enabled | LINK_EN_C (LINK_EN_C): Disabled | LINK_EN_D (LINK_EN_D): Disabled
i2ctransfer -f -y 2 w3@0x29 0x00 0x10 0x21 #// DEV : REG26 | RX_RATE_PHYA (RX_RATE_PHYA): 3
i2ctransfer -f -y 2 w3@0x29 0x00 0x18 0x01 #// TOP_CTRL : CTRL1 | RESET_ONESHOT_A (RESET_ONESHOT_A): Activated
i2ctransfer -f -y 2 w3@0x29 0x00 0x10 0x11 #// DEV : REG26 | RX_RATE_PHYB (RX_RATE_PHYB): 3
i2ctransfer -f -y 2 w3@0x29 0x00 0x18 0x03 #// TOP_CTRL : CTRL1 | RESET_ONESHOT_B (RESET_ONESHOT_B): Activated
sleep 0.12 #// 120 msec delay
#// Link Initialization for Deserializer
i2ctransfer -f -y 2 w3@0x29 0x00 0x06 0xF3 #// DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | (Default) LINK_EN_B (LINK_EN_B): Enabled | (Default) LINK_EN_C (LINK_EN_C): Disabled | (Default) LINK_EN_D (LINK_EN_D): Disabled
#i2ctransfer -f -y 2 w3@0x29 0x00 0x03 0xFA #// DEV : REG3 | (Default) DIS_REM_CC_A (GMSL Link A I2C Port 0): Enabled | (Default) DIS_REM_CC_B (GMSL Link B I2C Port 0): Enabled | DIS_REM_CC_C (GMSL Link C I2C Port 0): Disabled | DIS_REM_CC_D (GMSL Link D I2C Port 0): Disabled
sleep 0.12 #// 120 msec delay
#// Video Transmit Configuration for Serializer(s)
i2ctransfer -f -y 2 w3@0x40 0x00 0x02 0x03 #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
i2ctransfer -f -y 2 w3@0x42 0x00 0x02 0x03 #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
#// 
#// INSTRUCTIONS FOR GMSL-A SERIALIZER MAX96717F
#// 
#// MIPI D-PHY Configuration
i2ctransfer -f -y 2 w3@0x40 0x03 0x30 0x00 #// MIPI_RX : MIPI_RX0 | (Default) RSVD (Port Configuration): 1x4
i2ctransfer -f -y 2 w3@0x40 0x03 0x83 0x00 #// MIPI_RX_EXT : EXT11 | Tun_Mode (Tunnel Mode): Disabled
i2ctransfer -f -y 2 w3@0x40 0x03 0x31 0x30 #// MIPI_RX : MIPI_RX1 | (Default) ctrl1_num_lanes (Port B - Lane Count): 4
i2ctransfer -f -y 2 w3@0x40 0x03 0x32 0xE0 #// MIPI_RX : MIPI_RX2 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
i2ctransfer -f -y 2 w3@0x40 0x03 0x33 0x04 #// MIPI_RX : MIPI_RX3 | (Default) phy2_lane_map (Lane Map - PHY2 D0): Lane 0 | (Default) phy2_lane_map (Lane Map - PHY2 D1): Lane 1
i2ctransfer -f -y 2 w3@0x40 0x03 0x34 0x00 #// MIPI_RX : MIPI_RX4 | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal
i2ctransfer -f -y 2 w3@0x40 0x03 0x35 0x00 #// MIPI_RX : MIPI_RX5 | (Default) phy2_pol_map (Polarity - PHY2 Lane 0): Normal | (Default) phy2_pol_map (Polarity - PHY2 Lane 1): Normal | (Default) phy2_pol_map (Polarity - PHY2 Clock Lane): Normal
#// Controller to Pipe Mapping Configuration
i2ctransfer -f -y 2 w3@0x40 0x03 0x08 0x64 #// FRONTTOP : FRONTTOP_0 | (Default) RSVD (CLK_SELZ): Port B | (Default) START_PORTB (START_PORTB): Enabled
i2ctransfer -f -y 2 w3@0x40 0x03 0x11 0x40 #// FRONTTOP : FRONTTOP_9 | (Default) START_PORTBZ (START_PORTBZ): Start Video
i2ctransfer -f -y 2 w3@0x40 0x03 0x18 0x6C #// FRONTTOP : FRONTTOP_16 | mem_dt1_selz (mem_dt1_selz): 0x6C
#// Double Mode Configuration
i2ctransfer -f -y 2 w3@0x40 0x01 0x10 0x60 #// VID_TX__Z : VIDEO_TX0 | AUTO_BPP (AUTO_BPP Pipe Z): Use bpp from bpp register
i2ctransfer -f -y 2 w3@0x40 0x01 0x11 0x58 #// VID_TX__Z : VIDEO_TX1 | (Default) BPP (BPP Pipe Z): 0x18
i2ctransfer -f -y 2 w3@0x40 0x01 0x12 0x08 #// VID_TX__Z : VIDEO_TX2 | RSVD (DRIFT_DET_EN Pipe Z): Disable PCLK frequency drift detection
i2ctransfer -f -y 2 w3@0x40 0x03 0x13 0x40 #// FRONTTOP : FRONTTOP_11 | bpp12dblz (bpp12dblz): Send 12-bit pixels as 24-bit
i2ctransfer -f -y 2 w3@0x40 0x03 0x1E 0x38 #// FRONTTOP : FRONTTOP_22 | (Default) soft_bppz (soft_bppz): 0x18 | soft_bppz_en (soft_bppz_en): Software override enabled
#// Pipe Configuration
i2ctransfer -f -y 2 w3@0x40 0x00 0x5B 0x00 #// CFGV__VIDEO_Z : TX3 | TX_STR_SEL (TX_STR_SEL Pipe Z): 0x0
#// 
#// INSTRUCTIONS FOR GMSL-B SERIALIZER MAX96717F
#// 
#// MIPI D-PHY Configuration
i2ctransfer -f -y 2 w3@0x42 0x03 0x30 0x00 #// MIPI_RX : MIPI_RX0 | (Default) RSVD (Port Configuration): 1x4
i2ctransfer -f -y 2 w3@0x42 0x03 0x83 0x00 #// MIPI_RX_EXT : EXT11 | Tun_Mode (Tunnel Mode): Disabled
i2ctransfer -f -y 2 w3@0x42 0x03 0x31 0x30 #// MIPI_RX : MIPI_RX1 | (Default) ctrl1_num_lanes (Port B - Lane Count): 4
i2ctransfer -f -y 2 w3@0x42 0x03 0x32 0xE0 #// MIPI_RX : MIPI_RX2 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
i2ctransfer -f -y 2 w3@0x42 0x03 0x33 0x04 #// MIPI_RX : MIPI_RX3 | (Default) phy2_lane_map (Lane Map - PHY2 D0): Lane 0 | (Default) phy2_lane_map (Lane Map - PHY2 D1): Lane 1
i2ctransfer -f -y 2 w3@0x42 0x03 0x34 0x00 #// MIPI_RX : MIPI_RX4 | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal
i2ctransfer -f -y 2 w3@0x42 0x03 0x35 0x00 #// MIPI_RX : MIPI_RX5 | (Default) phy2_pol_map (Polarity - PHY2 Lane 0): Normal | (Default) phy2_pol_map (Polarity - PHY2 Lane 1): Normal | (Default) phy2_pol_map (Polarity - PHY2 Clock Lane): Normal
#// Controller to Pipe Mapping Configuration
i2ctransfer -f -y 2 w3@0x42 0x03 0x08 0x64 #// FRONTTOP : FRONTTOP_0 | (Default) RSVD (CLK_SELZ): Port B | (Default) START_PORTB (START_PORTB): Enabled
i2ctransfer -f -y 2 w3@0x42 0x03 0x11 0x40 #// FRONTTOP : FRONTTOP_9 | (Default) START_PORTBZ (START_PORTBZ): Start Video
i2ctransfer -f -y 2 w3@0x42 0x03 0x18 0x6C #// FRONTTOP : FRONTTOP_16 | mem_dt1_selz (mem_dt1_selz): 0x6C
#// Double Mode Configuration
i2ctransfer -f -y 2 w3@0x42 0x01 0x10 0x60 #// VID_TX__Z : VIDEO_TX0 | AUTO_BPP (AUTO_BPP Pipe Z): Use bpp from bpp register
i2ctransfer -f -y 2 w3@0x42 0x01 0x11 0x58 #// VID_TX__Z : VIDEO_TX1 | (Default) BPP (BPP Pipe Z): 0x18
i2ctransfer -f -y 2 w3@0x42 0x01 0x12 0x08 #// VID_TX__Z : VIDEO_TX2 | RSVD (DRIFT_DET_EN Pipe Z): Disable PCLK frequency drift detection
i2ctransfer -f -y 2 w3@0x42 0x03 0x13 0x40 #// FRONTTOP : FRONTTOP_11 | bpp12dblz (bpp12dblz): Send 12-bit pixels as 24-bit
i2ctransfer -f -y 2 w3@0x42 0x03 0x1E 0x38 #// FRONTTOP : FRONTTOP_22 | (Default) soft_bppz (soft_bppz): 0x18 | soft_bppz_en (soft_bppz_en): Software override enabled
#// Pipe Configuration
i2ctransfer -f -y 2 w3@0x42 0x00 0x5B 0x00 #// CFGV__VIDEO_Z : TX3 | TX_STR_SEL (TX_STR_SEL Pipe Z): 0x0
#// 
#// INSTRUCTIONS FOR DESERIALIZER MAX96712
#// 
#// Video Pipes And Routing Configuration
i2ctransfer -f -y 2 w3@0x29 0x00 0xF0 0x40 #// VIDEO_PIPE_SEL : VIDEO_PIPE_SEL_0 | (Default) VIDEO_PIPE_SEL_0 (Pipe 0 GMSL2 PHY): A | VIDEO_PIPE_SEL_0 (Pipe 0 Input Pipe): X | (Default) VIDEO_PIPE_SEL_1 (Pipe 1 GMSL2 PHY): B | VIDEO_PIPE_SEL_1 (Pipe 1 Input Pipe): X
i2ctransfer -f -y 2 w3@0x29 0x00 0xF4 0x03 #// VIDEO_PIPE_SEL : VIDEO_PIPE_EN | (Default) VIDEO_PIPE_EN (Video Pipe 0): Enabled | (Default) VIDEO_PIPE_EN (Video Pipe 1): Enabled | VIDEO_PIPE_EN (Video Pipe 2): Disabled | VIDEO_PIPE_EN (Video Pipe 3): Disabled | STREAM_SEL_ALL (Stream Select All): Disabled
#// Pipe to Controller Mapping Configuration
i2ctransfer -f -y 2 w3@0x29 0x09 0x0B 0x07 #// MIPI_TX__0 : MIPI_TX11 | MAP_EN_L (MAP_EN_L Pipe 0): 0x7
i2ctransfer -f -y 2 w3@0x29 0x09 0x0C 0x00 #// MIPI_TX__0 : MIPI_TX12 | (Default) MAP_EN_H (MAP_EN_H Pipe 0): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x0D 0x2C #// MIPI_TX__0 : MIPI_TX13 | MAP_SRC_0 (MAP_SRC_0 Pipe 0 DT): 0x2C | (Default) MAP_SRC_0 (MAP_SRC_0 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x0E 0x2C #// MIPI_TX__0 : MIPI_TX14 | MAP_DST_0 (MAP_DST_0 Pipe 0 DT): 0x2C | (Default) MAP_DST_0 (MAP_DST_0 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x0F 0x00 #// MIPI_TX__0 : MIPI_TX15 | (Default) MAP_SRC_1 (MAP_SRC_1 Pipe 0 DT): 0x0 | (Default) MAP_SRC_1 (MAP_SRC_1 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x10 0x00 #// MIPI_TX__0 : MIPI_TX16 | (Default) MAP_DST_1 (MAP_DST_1 Pipe 0 DT): 0x0 | (Default) MAP_DST_1 (MAP_DST_1 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x11 0x01 #// MIPI_TX__0 : MIPI_TX17 | MAP_SRC_2 (MAP_SRC_2 Pipe 0 DT): 0x1 | (Default) MAP_SRC_2 (MAP_SRC_2 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x12 0x01 #// MIPI_TX__0 : MIPI_TX18 | MAP_DST_2 (MAP_DST_2 Pipe 0 DT): 0x1 | (Default) MAP_DST_2 (MAP_DST_2 Pipe 0 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x2D 0x15 #// MIPI_TX__0 : MIPI_TX45 | MAP_DPHY_DEST_0 (MAP_DPHY_DST_0 Pipe 0): 0x1 | MAP_DPHY_DEST_1 (MAP_DPHY_DST_1 Pipe 0): 0x1 | MAP_DPHY_DEST_2 (MAP_DPHY_DST_2 Pipe 0): 0x1
i2ctransfer -f -y 2 w3@0x29 0x09 0x4B 0x07 #// MIPI_TX__1 : MIPI_TX11 | MAP_EN_L (MAP_EN_L Pipe 1): 0x7
i2ctransfer -f -y 2 w3@0x29 0x09 0x4C 0x00 #// MIPI_TX__1 : MIPI_TX12 | (Default) MAP_EN_H (MAP_EN_H Pipe 1): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x4D 0x2C #// MIPI_TX__1 : MIPI_TX13 | MAP_SRC_0 (MAP_SRC_0 Pipe 1 DT): 0x2C | (Default) MAP_SRC_0 (MAP_SRC_0 Pipe 1 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x4E 0x6C #// MIPI_TX__1 : MIPI_TX14 | MAP_DST_0 (MAP_DST_0 Pipe 1 DT): 0x2C | MAP_DST_0 (MAP_DST_0 Pipe 1 VC): 0x1
i2ctransfer -f -y 2 w3@0x29 0x09 0x4F 0x00 #// MIPI_TX__1 : MIPI_TX15 | (Default) MAP_SRC_1 (MAP_SRC_1 Pipe 1 DT): 0x0 | (Default) MAP_SRC_1 (MAP_SRC_1 Pipe 1 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x50 0x40 #// MIPI_TX__1 : MIPI_TX16 | (Default) MAP_DST_1 (MAP_DST_1 Pipe 1 DT): 0x0 | MAP_DST_1 (MAP_DST_1 Pipe 1 VC): 0x1
i2ctransfer -f -y 2 w3@0x29 0x09 0x51 0x01 #// MIPI_TX__1 : MIPI_TX17 | MAP_SRC_2 (MAP_SRC_2 Pipe 1 DT): 0x1 | (Default) MAP_SRC_2 (MAP_SRC_2 Pipe 1 VC): 0x0
i2ctransfer -f -y 2 w3@0x29 0x09 0x52 0x41 #// MIPI_TX__1 : MIPI_TX18 | MAP_DST_2 (MAP_DST_2 Pipe 1 DT): 0x1 | MAP_DST_2 (MAP_DST_2 Pipe 1 VC): 0x1
i2ctransfer -f -y 2 w3@0x29 0x09 0x6D 0x15 #// MIPI_TX__1 : MIPI_TX45 | MAP_DPHY_DEST_0 (MAP_DPHY_DST_0 Pipe 1): 0x1 | MAP_DPHY_DEST_1 (MAP_DPHY_DST_1 Pipe 1): 0x1 | MAP_DPHY_DEST_2 (MAP_DPHY_DST_2 Pipe 1): 0x1
#// Double Mode Configuration
i2ctransfer -f -y 2 w3@0x29 0x09 0x73 0x01 #// MIPI_TX__1 : MIPI_TX51 | ALT_MEM_MAP12 (ALT_MEM_MAP12 CTRL1): Alternate memory map enabled
#// MIPI D-PHY Configuration
i2ctransfer -f -y 2 w3@0x29 0x08 0xA0 0x08 #// MIPI_PHY : MIPI_PHY0 | phy_4x2 (Port Configuration): 1x4A + 2x2
i2ctransfer -f -y 2 w3@0x29 0x09 0x4A 0xD0 #// MIPI_TX__1 : MIPI_TX10 | (Default) CSI2_LANE_CNT (Port A - Lane Count): 4
i2ctransfer -f -y 2 w3@0x29 0x08 0xA3 0xE4 #// MIPI_PHY : MIPI_PHY3 | (Default) phy0_lane_map (Lane Map - PHY0 D0): Lane 0 | (Default) phy0_lane_map (Lane Map - PHY0 D1): Lane 1 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
i2ctransfer -f -y 2 w3@0x29 0x08 0xA5 0x00 #// MIPI_PHY : MIPI_PHY5 | (Default) phy0_pol_map (Polarity - PHY0 Lane 0): Normal | (Default) phy0_pol_map (Polarity - PHY0 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Clock Lane): Normal
i2ctransfer -f -y 2 w3@0x29 0x09 0x43 0x07 #// MIPI_TX__1 : MIPI_TX3 | DESKEW_INIT (Controller 1 Auto Initial Deskew): Disabled
i2ctransfer -f -y 2 w3@0x29 0x09 0x44 0x01 #// MIPI_TX__1 : MIPI_TX4 | DESKEW_PER (Controller 1 Periodic Deskew): Disabled
i2ctransfer -f -y 2 w3@0x29 0x1D 0x00 0xF4 #// (config_soft_rst_n - PHY1): 0x0
#// This is to set predefined (coarse) CSI output frequency
#// CSI Phy 1 is 1500 Mbps/lane.
i2ctransfer -f -y 2 w3@0x29 0x1D 0x00 0xF4 #// (Default) 
i2ctransfer -f -y 2 w3@0x29 0x04 0x18 0x2F #// (Default) 
i2ctransfer -f -y 2 w3@0x29 0x1D 0x00 0xF5 #// | (Default) (config_soft_rst_n - PHY1): 0x1
i2ctransfer -f -y 2 w3@0x29 0x08 0xA2 0x34 #// MIPI_PHY : MIPI_PHY2 | phy_Stdby_n (phy_Stdby_2): Put PHY2 in standby mode | phy_Stdby_n (phy_Stdby_3): Put PHY3 in standby mode
i2ctransfer -f -y 2 w3@0x29 0x04 0x0B 0x02 #// BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output enabled
#// Video Transmit Configuration for Serializer(s)
i2ctransfer -f -y 2 w3@0x40 0x00 0x02 0x43 #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled
i2ctransfer -f -y 2 w3@0x42 0x00 0x02 0x43 #// DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled

ADIApproved · Accepted Answer

1. CSI口没有输出，是从jetson的软件角度看没有数据，还是实测信号线上没有信号； 
 2. 检查数据格式是否匹配； 
 3. 可尝试使用MAX96724F等带有tunnel传输模式的DES。)

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max96717f与max96712传输数据问题

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