您好！我的应用场景是将域控制器上的解串器96712（96722）接收的4路环视YUV422 8bit数据从csi端口bypass至串行器96717再转发至另一个控制器的解串器96712（96722）。请问这个方案是否可行？
您好！我的应用场景是将域控制器上的解串器96712（96722）接收的4路环视YUV422 8bit数据从csi端口bypass至串行器96717再转发至另一个控制器的解串器96712（96722）。请问这个方案是否可行？
您好，我们目前也有个相似的使用 场景， 我们是max96724环出4个1080P yuv422的camera到max96717然后串化后给到另外的一个max96724，可以交换一些经验吗，目前我们是用Tunnel mode 环出的数据会有异常，使用 Pixel mode 96717总是报fifo overflow的问题
您好，我们目前也有个相似的使用 场景， 我们是max96724环出4个1080P yuv422的camera到max96717然后串化后给到另外的一个max96724，可以交换一些经验吗，目前我们是用Tunnel mode 环出的数据会有异常，使用 Pixel mode 96717总是报fifo overflow的问题
连接方式如图，红色箭头表示数据流方向，两个SoC是相同的：
配置数据流上第一个GMSL(9295-96724)配置为：（该配置下从Port A出来的数据显示正常）
## maxim 96724 <---------> maxim 9295a ## addr:0x27(7bit) addr:0x62(7bit) i2ctransfer -y 5 w3@0x62 0x00 0x10 0x80 sleep 3 i2ctransfer -y 5 w3@0x27 0x00 0x13 0x40 sleep 0.5 i2ctransfer -y 5 w3@0x27 0x09 0x0a 0xC0 #set csi lane num and vcx_en i2ctransfer -y 5 w3@0x27 0x09 0x4a 0xC0 i2ctransfer -y 5 w3@0x27 0x09 0x8a 0xC0 i2ctransfer -y 5 w3@0x27 0x09 0xca 0xC0 i2ctransfer -y 5 w3@0x27 0x09 0x39 0x50 i2ctransfer -y 5 w3@0x27 0x09 0x79 0x50 i2ctransfer -y 5 w3@0x27 0x09 0xb9 0x50 i2ctransfer -y 5 w3@0x27 0x09 0xf9 0x50 # i2ctransfer -y 5 w3@0x27 0x03 0x00 0x93 #enable gpio0_link A tx_en #change # i2ctransfer -y 5 w3@0x27 0x03 0x37 0x20 #enable gpio0_link B tx_en # i2ctransfer -y 5 w3@0x27 0x03 0x6d 0x20 #enable gpio0_link C tx_en # i2ctransfer -y 5 w3@0x27 0x03 0xa4 0x20 #enable gpio0_link D tx_en i2ctransfer -y 5 w3@0x27 0x03 0x13 0x83 #? set a readonly bit? i2ctransfer -y 5 w3@0x27 0x03 0x14 0xa6 #? set a readonly bit? i2ctransfer -y 5 w3@0x27 0x08 0xa3 0x4e #? set a readonly bit? #test start i2ctransfer -y 5 w3@0x27 0x09 0x03 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x43 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x83 0x00 i2ctransfer -y 5 w3@0x27 0x09 0xc3 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x04 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x44 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x84 0x00 i2ctransfer -y 5 w3@0x27 0x09 0xc4 0x00 #test end i2ctransfer -y 5 w3@0x62 0x00 0x10 0x80 sleep 0.5 i2ctransfer -y 5 w3@0x27 0x09 0x0B 0x07 # enable 3 mappings for pipeline 0 i2ctransfer -y 5 w3@0x27 0x09 0x2D 0x15 # map to MIPI Controller 1 i2ctransfer -y 5 w3@0x27 0x09 0x0D 0x1e i2ctransfer -y 5 w3@0x27 0x09 0x0E 0x1e # map to VC0 i2ctransfer -y 5 w3@0x27 0x09 0x0F 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x10 0x00 i2ctransfer -y 5 w3@0x27 0x09 0x11 0x01 i2ctransfer -y 5 w3@0x27 0x09 0x12 0x01 # i2ctransfer -y 5 w3@0x27 0x09 0x4B 0x07 # enable 3 mappings for pipeline 1 # i2ctransfer -y 5 w3@0x27 0x09 0x6D 0x15 # map to MIPI Controller 1 # i2ctransfer -y 5 w3@0x27 0x09 0x4D 0x1e # i2ctransfer -y 5 w3@0x27 0x09 0x4E 0x5e # map to VC1 # i2ctransfer -y 5 w3@0x27 0x09 0x4F 0x00 # frame start # i2ctransfer -y 5 w3@0x27 0x09 0x50 0x40 # i2ctransfer -y 5 w3@0x27 0x09 0x51 0x01 # i2ctransfer -y 5 w3@0x27 0x09 0x52 0x41 # i2ctransfer -y 5 w3@0x27 0x09 0x8B 0x07 # enable 3 mappings for pipeline 2 # i2ctransfer -y 5 w3@0x27 0x09 0xAD 0x15 # map to MIPI Controller 1 # i2ctransfer -y 5 w3@0x27 0x09 0x8D 0x1e # i2ctransfer -y 5 w3@0x27 0x09 0x8E 0x9e # map to VC2 # i2ctransfer -y 5 w3@0x27 0x09 0x8F 0x00 # i2ctransfer -y 5 w3@0x27 0x09 0x90 0x80 # i2ctransfer -y 5 w3@0x27 0x09 0x91 0x01 # i2ctransfer -y 5 w3@0x27 0x09 0x92 0x81 # i2ctransfer -y 5 w3@0x27 0x09 0xCB 0x07 # enable 3 mappings for pipeline 3 # i2ctransfer -y 5 w3@0x27 0x09 0xED 0x15 # map to MIPI Controller 1 # i2ctransfer -y 5 w3@0x27 0x09 0xCD 0x1e # i2ctransfer -y 5 w3@0x27 0x09 0xCE 0xde # map to VC3 # i2ctransfer -y 5 w3@0x27 0x09 0xCF 0x00 # i2ctransfer -y 5 w3@0x27 0x09 0xD0 0xC0 # i2ctransfer -y 5 w3@0x27 0x09 0xD1 0x01 # i2ctransfer -y 5 w3@0x27 0x09 0xD2 0xC1 i2ctransfer -y 5 w3@0x27 0x04 0x0B 0x00 #disabel csi_out_en # i2ctransfer -y 5 w3@0x27 0x00 0x06 0xf1 # sleep 0.5 # i2ctransfer -y 5 w3@0x62 0x00 0x00 0x40 # i2ctransfer -y 5 w3@0x27 0x00 0x06 0xf2 # sleep 0.5 # i2ctransfer -y 5 w3@0x62 0x00 0x00 0x42 # i2ctransfer -y 5 w3@0x27 0x00 0x06 0xf4 # sleep 0.5 # i2ctransfer -y 5 w3@0x62 0x00 0x00 0x44 # i2ctransfer -y 5 w3@0x27 0x00 0x06 0xf8 # sleep 0.5 # i2ctransfer -y 5 w3@0x62 0x00 0x00 0x46 i2ctransfer -y 5 w3@0x27 0x00 0x06 0xff #enable all links #change sleep 0.5 i2ctransfer -y 5 w3@0x27 0x00 0x10 0x22 #set GMSL rate i2ctransfer -y 5 w3@0x27 0x00 0x11 0x22 #set GMSL rate i2ctransfer -y 5 w3@0x27 0x00 0x18 0x0f #reset all links onshot #change sleep 0.5 i2ctransfer -y 5 w3@0x27 0x00 0xF0 0x62 #select pipe i2ctransfer -y 5 w3@0x27 0x00 0xF1 0xEA i2ctransfer -y 5 w3@0x27 0x00 0xF4 0x0f #enable all pipe #change sleep 0.5 # i2ctransfer -y 5 w3@0x27 0x01 0x06 0x0A #enable max96712 Link A heartbeat # i2ctransfer -y 5 w3@0x27 0x01 0x18 0x0A #enable max96712 Link B heartbeat # i2ctransfer -y 5 w3@0x27 0x01 0x2A 0x0A #enable max96712 Link C heartbeat # i2ctransfer -y 5 w3@0x27 0x01 0x3C 0x0A #enable max96712 Link D heartbeat #hold dpll in reset before changing the rate i2ctransfer -y 5 w3@0x27 0x1C 0x00 0xF4 i2ctransfer -y 5 w3@0x27 0x1D 0x00 0xF4 i2ctransfer -y 5 w3@0x27 0x1E 0x00 0xF4 i2ctransfer -y 5 w3@0x27 0x1F 0x00 0xF4 #set phy dpll frequency is max i2ctransfer -y 5 w3@0x27 0x04 0x15 0x39 i2ctransfer -y 5 w3@0x27 0x04 0x18 0x39 i2ctransfer -y 5 w3@0x27 0x04 0x1B 0x39 i2ctransfer -y 5 w3@0x27 0x04 0x1E 0x39 #release dpll in reset after changing the rate i2ctransfer -y 5 w3@0x27 0x1C 0x00 0xF5 i2ctransfer -y 5 w3@0x27 0x1D 0x00 0xF5 i2ctransfer -y 5 w3@0x27 0x1E 0x00 0xF5 i2ctransfer -y 5 w3@0x27 0x1F 0x00 0xF5 # i2ctransfer -y 5 w3@0x27 0x04 0xA2 0x00 #set FSYNC master link as Video0, # i2ctransfer -y 5 w3@0x27 0x04 0xAF 0xCF #set FSYNC GPIOtype as GMSL2 type, and enable crystal oscillator for generating FS, and enable all links use FS # i2ctransfer -y 5 w3@0x27 0x04 0xA7 0x0C #High byte of number of PLCK cycles # i2ctransfer -y 5 w3@0x27 0x04 0xA6 0xB7 #Middle byte of number of PLCK cycles # i2ctransfer -y 5 w3@0x27 0x04 0xA5 0x35 #Low byte of number of PLCK cycles # i2ctransfer -y 5 w3@0x27 0x04 0xB1 0x10 #use max96712 GPIO2 for FSYNC transmission # i2ctransfer -y 5 w3@0x62 0x02 0xD5 0x02 #set all max9295a GPIO7 for recieve FSYNC from max96712 GPIO2 # i2ctransfer -y 5 w3@0x62 0x02 0xD3 0x84 #enbale all max9295a GPIO7 GPIO_RX_EN # i2ctransfer -y 5 w3@0x62 0x02 0xD8 0x02 #set all max9295a GPIO8 for recieve FSYNC from max96712 GPIO2 # i2ctransfer -y 5 w3@0x62 0x02 0xD6 0x84 #enbale all max9295a GPIO7 GPIO_RX_EN # i2ctransfer -y 5 w3@0x27 0x04 0xA0 0x04 #set Frame Synchronization Method as manual and FSYNC_MODE as Frame sync generation is on. GPIO is used as FSYNC output and drives a slave device # sleep 0.5 i2ctransfer -y 5 w3@0x27 0x08 0xA0 0x04 #set phy mode 2x4 i2ctransfer -y 5 w3@0x27 0x08 0xA3 0xE4 #set phy lane map i2ctransfer -y 5 w3@0x27 0x08 0xA4 0xE4 i2ctransfer -y 5 w3@0x27 0x08 0xA2 0xF4 sleep 0.5 i2ctransfer -y 5 w3@0x62 0x03 0x30 0x00 i2ctransfer -y 5 w3@0x62 0x03 0x32 0xE4 i2ctransfer -y 5 w3@0x62 0x03 0x33 0xE4 i2ctransfer -y 5 w3@0x62 0x02 0xBE 0x10 i2ctransfer -y 5 w3@0x62 0x03 0x18 0x5E i2ctransfer -y 5 w3@0x62 0x02 0xBE 0x80 sleep 1 i2ctransfer -y 5 w3@0x62 0x02 0xBE 0x90 i2ctransfer -y 5 w3@0x62 0x03 0x31 0x33 sleep 0.5 sleep 0.5 i2ctransfer -y 5 w3@0x1a 0x8A 0x01 0x00 sleep 0.5 i2ctransfer -y 5 w3@0x1a 0xBF 0x14 0x00 sleep 0.5 i2ctransfer -y 5 w3@0x1a 0x8A 0xF0 0x00 sleep 0.5 i2ctransfer -y 5 w3@0x1a 0x8A 0x01 0x80 sleep 0.5 i2ctransfer -y 5 w3@0x27 0x00 0x18 0x0f #change i2ctransfer -y 5 w3@0x27 0x08 0xA9 0xC8 # i2ctransfer -y 5 w3@0x4e 0x09 0x71 0x8F # concatenation sleep 0.5 i2ctransfer -y 5 w3@0x27 0x04 0x0B 0x02 i2ctransfer -y 5 w3@0x27 0x08 0xA0 0x84
第二个GMSL(96717-96724)配置为
### maxim 96717 <----------> maxim 96724 ### addr:0x40(7bit) addr:0x4e(7bit) # i2ctransfer -y 5 w3@0x40 0x00 0x10 0x80 # i2ctransfer -y 5 w3@0x4e 0x00 0x13 0x40 sleep 1 i2ctransfer -y 5 w3@0x40 0x00 0x1 0x08 sleep 1 i2ctransfer -y 5 w3@0x4e 0x04 0x0B 0x00 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0x06 0xff sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0x10 0x22 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0x18 0x0f sleep 0.2 sleep 0.2 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x00 0x02 0x03 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x30 0x00 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x83 0x80 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x31 0x30 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x32 0xE0 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x33 0x04 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x34 0x00 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x35 0x00 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x08 0x64 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x11 0x40 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x03 0x15 0x00 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x00 0x5B 0x02 sleep 0.2 sleep 0.2 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0xf0 0x62 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0xf1 0xea sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x00 0xf4 0x0f sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x08 0xa0 0x04 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x09 0x4a 0xc0 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x09 0x43 0x07 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x09 0x44 0x01 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x1d 0x00 0xf4 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x04 0x18 0x39 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x1d 0x00 0xf5 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x08 0xca 0x55 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x09 0x39 0x10 i2ctransfer -y 5 w3@0x4e 0x09 0x79 0x10 i2ctransfer -y 5 w3@0x4e 0x09 0xb9 0x10 i2ctransfer -y 5 w3@0x4e 0x09 0xf9 0x10 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x09 0x36 0x09 i2ctransfer -y 5 w3@0x4e 0x09 0x76 0x09 i2ctransfer -y 5 w3@0x4e 0x09 0xb6 0x09 i2ctransfer -y 5 w3@0x4e 0x09 0xf6 0x09 sleep 0.2 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x04 0x0b 0x02 sleep 0.2 i2ctransfer -y 5 w3@0x40 0x00 0x02 0x43 sleep 0.2 i2ctransfer -y 5 w3@0x4e 0x08 0xa0 0x84 sleep 0.2 # i2ctransfer -y 5 w3@0x4e 0x00 0x03 0xff sleep 0.2 sleep 0.2 i2ctransfer -y 5 w2@0x4e 0x01 0xdc r1 sleep 0.2 i2ctransfer -y 5 w2@0x40 0x01 0x12 r1 sleep 0.2
图像输入为UYVY 1920*1280@30fps 一路（四路也是一样的现象）
第一个96724的phy dpll frequency为1500MHz时，第二个96724收到的环出图像为下图，似乎更正确了一部分，但是在四路情况下第一个96724的dpll最低为1500MHz，再低传输就不正确了
按照user guide里这部分计算
video payload = 1937*1297 * 30(fps) * 16(bpp) * 4 (numbers of camera) = 4,823,594,880 < 5.2Gbps的，GMSL的理论带宽应该是足够的吧
但是下面这图中说tunnel模式bpp固定为24，是否是导致该情况的原因呢
