AD9467 输出电平标准为"LVDS"，是否支持连接FPGA BANK1.8V，引脚约束为"LVDS"

Question

我已经看过AD9467的评估板在ZEDboard和KC705的引脚约束为"LVDS_25",对应FPGA的BANK VCCO供电2.5V，但是现在我的项目中FPGA BANK 的VCCO供电是1.8V，我对其做引脚约束为"LDVS"可行吗？

EmmaChen · Accepted Answer

I am no FPGA expert, but i believe that LVDS is an ANSI standard. The standard depends on the differential swing of signals around a common mode voltage of ~1.2V. See datasheet excerpt below: 
 
 So if your FPGA supports this mode, then the AD9467 should be able to send data to your FPGA. 
 答案来源： The output of the AD9467 is LVDS level standard... | EngineerZone)

AD9467 输出电平标准为"LVDS"，是否支持连接FPGA BANK1.8V，引脚约束为"LVDS"

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